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quad 16-bit,1 gsps, txdac+ digital-to-analog converter ad9148 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features single-carrier w-cdma aclr = 80 dbc at 150 mhz if channel-to-channel isolation > 90 db analog output adjustable 8.7 ma to 31.7 ma r l = 25 to 50 novel 2, 4, and 8 interpolator eases data interface on-chip fine complex nco allows carrier placement anywhere in dac bandwidth high performance, low noise pll clock multiplier multiple chip synchronization interface programmable digital inverse sinc filter auxiliary dacs allow for offset control gain dacs allow for i and q gain matching programmable i and q phase compensation digital gain control flexible lvds digital i/f supports 32- or 16-bit bus width 196-ball csp_bga, 12 mm 12 mm applications wireless infrastructure lte, td-scdma, wimax, w-cdma, cdma2000, gsm mimo/transmit diversity digital high or low if synthesis general description the ad9148 is a quad, 16-bit, high dynamic range, digital-to- analog converter (dac) that provides a sample rate of 1000 msps. this device includes features optimized for direct conversion transmit applications, including gain, phase, and offset compen- sation. the dac outputs are optimized to interface seamlessly with analog quadrature modulators such as the adl5371 / adl5372 / adl5373 / adl5374 / adl5375 . a serial peripheral interface (spi) is provided for programming of the internal device parameters. full-scale output current can be programmed over a range of 10 ma to 30 ma. the device operates from 1.8 v and 3.3 v supplies for a total power consumption of 3 w at the maximum sample rate. the ad9148 is enclosed in a 196-ball chip scale package ball grid array with the option of an attached heat spreader. product highlights 1. low noise and intermodulation distortion (imd) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. 2. a proprietary dac output switching technique enhances dynamic performance. 3. the current outputs are easily configured for various single-ended or differential circuit topologies. 4. the lvds data input interface includes fifo to ease input timing. typical signal chain fpga/asic/dsp notes 1. aqm = analog quadrature modulator. dc complex baseband complex if rf f if lo f if dac1 dac2 digital interpolation filters post dac analog filter dac3 dac4 post dac aqm lo aqm 2 2 2 2 2 2 2 2 2 2 2 2 pa pa lo 08910-001 figure 1.
ad9148 rev. 0 | page 2 of 76 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 typical signal chain ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 input/output signal specifications ............................................ 5 digital input data timing specifications ................................. 6 ac specifications .......................................................................... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 maximum safe power dissipation ............................................. 8 esd caution .................................................................................. 8 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 14 terminology .................................................................................... 20 serial peripheral interface ............................................................. 21 general operation of the serial interface ............................... 21 data format ................................................................................ 21 spi pin descriptions .................................................................. 21 spi options ................................................................................. 22 spi register map ............................................................................. 23 spi register descriptions .......................................................... 25 input data ports .............................................................................. 39 dual-port mode .......................................................................... 39 single-port mode ........................................................................ 39 byte mode .................................................................................... 40 data interface options .............................................................. 40 frame input levels ......................................................................... 41 frame receiver input voltage swing example ....................... 41 fifo operation .............................................................................. 42 synchronizing and resetting the fifo ................................... 43 monitoring the fifo status ...................................................... 44 device synchronization ................................................................. 45 synchronizing multiple devices .............................................. 45 synchronization with clock multiplication ............................... 45 synchronization with direct clocking .................................... 47 additional synchronization features ...................................... 48 interface timing ............................................................................. 49 digital data path ............................................................................ 50 premodulation ............................................................................ 50 programmable inverse sinc filter ............................................ 50 interpolation filters ................................................................... 51 fine modulation ......................................................................... 54 quadrature phase correction ................................................... 55 dc offset correction ................................................................ 55 digital gain control .................................................................. 55 clock generation ........................................................................... 56 dac input clock configurations ............................................ 56 driving the clk_x and refclk_x inputs ............................ 56 direct clocking .......................................................................... 56 clock multiplication .................................................................. 57 analog outputs............................................................................... 59 transmit dac operation .......................................................... 59 auxiliary dac operation ......................................................... 60 interfacing to modulators ......................................................... 61 device power dissipation .............................................................. 63 temperature sensor ....................................................................... 65 interrupt request operation ........................................................ 66 interrupt service routine .......................................................... 66 interface timing validation .......................................................... 67 sed operation ............................................................................ 67 sed example .............................................................................. 67 test access port .............................................................................. 68 example start-up routine ............................................................ 71 derived pll settings ................................................................. 71 derived nco settings ............................................................... 71 start-up sequence ...................................................................... 71 device verification sequence ................................................... 71 outline dimensions ....................................................................... 72 ordering guide .......................................................................... 73 revision history 6/10revision 0: initial version
ad9148 rev. 0 | page 3 of 76 functional block diagram fifo data receiver 310mhz 310mhz 310mhz/620mhz 500mhz/1ghz 500mhz/1ghz i offset q offset f s /2 mod 1.2ghz 1ghz 2 2 i gain q gain 2 2 2 2 fifo i offset cos phase correction sin q offset gain/ offset_ctrl sinc ?1 sinc ?1 sinc ?1 sinc ?1 2 2 i gain q gain 2 2 2 internal clock timing and contro l logic 2 hb3_en hb3_clk hb2_en hb2_clk hb1_en hb1_clk invsine_en premod_en premod_clk mode sdo sdio sclk cs irq reset filter coefficient 16-bit dac1 16-bit dac2 32-bit nco 16-bit dac3 16-bit dac4 gain gain aux1 aux2 gain gain aux3 aux4 dac_clk sync reference bias pll_ctrl clock multiplier (2 ? 16) multi-chip sync power-on reset serial in/out port programming registers framea_p/ framea_n frameb_p/ frameb_n dcia_p/ dcia_n dcib_p/ dcib_n b[15:0]_p/ b[15:0]_n a[15:0]_p/ a[15:0]_n 16 16 iout1_p iout1_n aux1_p aux1_n iout2_p iout2_n aux2_p aux2_n iout3_p iout3_n aux3_p aux3_n iout4_p iout4_n aux4_p aux4_n vref i120 clk_p clk_n refclk_p/ sync_p refclk_n/ sync_n 08910-002 f s /2 mod f s /2 mod f s /2 mod figure 2.
ad9148 rev. 0 | page 4 of 76 specifications dc specifications t min to t max , avdd33 = 3.3 v, iovdd = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. table 1. parameter min typ max unit resolution 16 bits accuracy differential nonlinearity (dnl) 2.1 lsb integral nonlinearity (inl) 3.7 lsb main dac outputs offset error 0.001 % fsr gain error (with internal reference) 2 % fsr full-scale output current 1 8.66 20.2 31.66 ma output compliance range ?1.0 +1.0 v output resistance 10 m gain dac monotonicity guaranteed settling time to within 0.5 lsb 20 ns temperature drift main dac offset 0.04 ppm/c main dac gain 100 ppm/c reference voltage 30 ppm/c reference internal reference voltage 1.2 v output resistance 5 k analog supply voltages avdd33 3.13 3.3 3.47 v cvdd18 1.71 1.8 1.89 v digital supply voltages iovdd 1.71 1.8/3.3 3.47 v dvdd18 1.71 1.8 1.89 v power consumption (nco off, pll disabled, and sinc ?1 filter bypassed, unless otherwise noted) 1 mode, f dac = 300 msps, f interface = 600 msps 0.79 w 2 mode, f dac = 500 msps, f interface = 500 msps 1.49 w 4 mode, f dac = 800 msps, f interface = 400 msps 2.18 w 4 mode, f dac = 800 msps, f interface = 400 msps, nco on 2.47 w 4 mode, f dac = 800 msps, f interface = 400 msps, pll enabled 2.26 w 4 mode, f dac = 800 msps, f interface = 400 msps, sinc ?1 filter enabled 2.44 w 8 mode, f dac = 800 msps, f interface = 200 msps 2.01 2.16 w avdd33 368 373 mw cvdd18 261 280 mw iovdd 0.8 1.6 mw dvdd18 1377 1504 mw power-down mode 1 12 mw operating range ?40 +25 +85 c 1 based on a 10 k external resistor.
ad9148 rev. 0 | page 5 of 76 input/output signal specifications t min to t max , avdd33 = 3.3 v, iovdd = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. lvds driver and receiver are compliant to the ieee-1596 reduced range link, unless otherwise noted. table 2. parameter min typ max unit cmos input logic level (sclk, sdio, cs , reset , tms, tdi, tck) input v in logic high (iovdd = 1.8 v) 1.2 v input v in logic high (iovdd = 3.3 v) 2.0 v input v in logic low (iovdd = 1.8 v) 0.6 v input v in logic low (iovdd = 3.3 v) 0.8 v cmos output logic level (sdio, sdo, irq , pll_lock, tdo) output v out logic high (iovdd = 1.8 v) 1.4 v output v out logic high (iovdd = 3.3 v) 2.4 v output v out logic low (iovdd = 1.8 v) 0.4 v output v out logic low (iovdd = 3.3 v) 0.4 v lvds receiver inputs (a[15:0]_x, b[15:0]_x, dcia_x, dcib_x) input voltage range, v ia or v ib 825 1575 mv input differential threshold, v idth ?100 +100 mv input differential hysteresis, v idthh to v idthl 20 mv receiver differential input impedance, r in 80 120 lvds input rate, f interface (see table 4 ) 1200 msps lvds receiver inputs (framea_x, frameb_x) 1 input high voltage, v ia or v ib 1.225 1.575 v input low voltage, v ia or v ib 0.825 1.125 v dac clock input (clk_p, clk_n) differential peak-to-peak voltage 100 500 2000 mv common-mode voltage (self-biasing, ac-coupled) 1.25 v maximum clock rate 1000 msps reference clock input (refclk_x/sync_x) differential peak-to-peak voltage 100 500 2000 mv common-mode voltage (self-biasing, ac-coupled) 1.25 v maximum clock rate 500 msps minimum clock rate (pll enabled) loop divider = /2 125 msps loop divider = /4 62.5 msps loop divider = /8 31.25 msps loop divider = /16 15.625 msps serial peripheral interface maximum clock rate (sclk) 40 mhz minimum pulse width high (t pwh ) 12.5 ns minimum pulse width low (t pwl ) 12.5 ns set-up time, sdi to sclk (t ds ) 1.9 ns hold time, sdi to sclk (t dh ) 0.2 ns data valid, sdo to sclk (t dv ) 23 ns setup time, cs to sclk (t dcsb ) 1.4 ns 1 for more information on the framea_x and frameb_x levels, refer to the frame input levels section.
ad9148 rev. 0 | page 6 of 76 digital input data timing specifications table 3. parameter min typ max unit latency (dacclk cycles) 1 interpolation (with or without coarse modulation) 64 cycles 2 interpolation (with or without coarse modulation) 125 cycles 4 interpolation (with or without coarse modulation) 254 cycles 8 interpolation (with or without coarse modulation) 508 cycles inverse sinc (1 interpolation) 10 cycles inverse sinc (2 interpolation) 20 cycles inverse sinc (4 interpolation) 40 cycles inverse sinc (8 interpolation) 80 cycles fine modulation 12 cycles powerCup time 100 ms table 4. maximum rate maximum rate (msps) interface mode f interface f data f hb1 f hb2 f hb3 f dac dual port mode 620 310 620 1000 1000 1000 single port mode or byte mode 1200 300 600 1000 1000 1000 fifo a fifo b 2 2 2 clk generator and distributor f interface f data f hb1 f hb2 f hb3 f dac dac1 and dac2 dac3 and dac4 32 32 32 dcia dacclk data port a data port b data assembler input latch dcib data assembler input latch r e a d p t r a r e a d p t r b write ptr a write ptr b 32 32 32 interface mode one dci datapath datapath 2 2 2 08910-003 figure 3. defining maximum rates
ad9148 rev. 0 | page 7 of 76 ac specifications t min to t max , avdd33 = 3.3 v, iovdd = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. table 5. parameter min typ max unit spurious-free dynamic range (sfdr) f dac = 400 msps, f out = 80 mhz 72 dbc f dac = 600 msps, f out = 100 mhz 67 dbc f dac = 1000 msps, f out = 100 mhz 65 dbc two-tone intermodulation distortion (imd) f dac = 400 msps, f out = 100 mhz 85 dbc f dac = 600 msps, f out = 120 mhz 82 dbc f dac = 1000 msps, f out = 150 mhz 76 dbc noise spectral density (nsd) eight-tone, 500 khz tone spacing f dac = 200 msps, f out = 80 mhz ?160 dbm/hz f dac = 400 msps, f out = 100 mhz ?161 dbm/hz f dac = 800 msps, f out = 100 mhz ?162.5 dbm/hz w-cdma adjacent channel leakage ratio (aclr), single carrier f dac = 737.28 msps, f out = 100 mhz, pll off ?81 dbc f dac = 737.28 msps, f out = 100 mhz, pll on ?78 dbc f dac = 737.28 msps, f out = 200 mhz, pll off ?79 dbc f dac = 737.28 msps, f out = 200 mhz, pll on ?72.5 dbc w-cdma alternate channel leakage ratio, single carrier f dac = 737.28 msps, f out = 100 mhz, pll off ?87 dbc f dac = 737.28 msps, f out = 100 mhz, pll on ?83 dbc f dac = 737.28 msps, f out = 200 mhz, pll off ?84 dbc f dac = 737.28 msps, f out = 200 mhz, pll on ?80.5 dbc
ad9148 rev. 0 | page 8 of 76 absolute maximum ratings table 7. thermal resistance table 6. parameter with respect to rating avdd33, iovdd agnd, dgnd, cgnd ?0.3 v to +3.6 v dvdd18, cvdd18 agnd, dgnd, cgnd ?0.3 v to +2.10 v agnd dgnd, cgnd ?0.3 v to +0.3 v dgnd agnd, cgnd ?0.3 v to +0.3 v cgnd agnd, dgnd ?0.3 v to +0.3 v i120, vref agnd ?0.3 v to avdd33 + 0.3 v iout1_p, iout1_n, iout2_p, iout2_n, iout3_p, iout3_n, iout4_p, iout4_n agnd ?1.0 v to avdd33 + 0.3 v a15_p to a0_p, a15_n to a0_n, b15_p to b0_p, b15_n, b0_n dgnd ?0.3 v to dvdd18 + 0.3 v dcia_p, dcia_n, framea_p, framea_n, dcib_p, dcib_n, frameb_p, frameb_n dgnd ?0.3 v to dvdd18+ 0.3 v clk_p, clk_n, refclk_p, refclk_n cgnd ?0.3 v to cvdd18 + 0.3 v csb, sclk, sdio, sdo, tdo, tdi, tck, tms, reset , irq , pll_lock dgnd ?0.3 v to iovdd + 0.3 v junction temperature 125c storage temperature range ?65c to +150c package type ja jb jc unit notes 196-ball csp_bga 24.7 12.6 5.7 c/w 4-layer board, 25 pcb vias 19.2 10.9 5.3 c/w 8-layer board, 25 pcb vias 18.1 10.5 5.3 c/w 10-layer board, 25 pcb vias 18.0 10.5 5.3 c/w 12-layer board, 25 pcb vias 196-ball bga_ed 20.9 8.6 3.1 c/w 4-layer board, 25 pcb vias 16.2 7.7 3.1 c/w 8-layer board, 25 pcb vias 15.2 7.4 3.1 c/w 10-layer board, 25 pcb vias 15.0 7.4 3.1 c/w 12-layer board, 25 pcb vias maximum safe power dissipation the maximum junction temperature for the ad9148 is 125c. with the thermal resistance of the molded package (csp_bga) given for a 12 layer board, the maximum power that can be dissipated in this package can be calculated as ( ) () w tt power ja a j max 22.2 0.18 85125 = ? = ? = to increase the maximum power, the ad9148 is available in a second package option (bga_ed), which includes a heat spreader on top of the package. also, an external heat sink can be attached to the top of the ad9148 csp_bga package. the adjusted maximum power for each of these conditions is shown in table 8 . with the thermal resistance of the heat spreader package (bga_ed) given for a 12-layer board, the maximum power that can be dissipated in this packag e can be calculated as stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( ) () w tt power ja a j max 67.2 0.15 85125 = ? = ? = to increase the maximum power, an external heat sink can be attached to the top of the ad9148 bga_ed package. the adjusted maximum power for an external heat sink is shown in table 8 . to aid in the selection of package, the maximum f dac rate for a given power dissipation over several operating conditions is shown in table 9 . the maximum f dac rate applies to all interpolation rates. note that, if the programmable inverse sinc filter is enabled, the maximum f dac rate specified in table 9 decreases. thermal resistance typical ja , jb , and jc are specified vs. the number of pcb layers in still air for each package offering. airflow increases heat dissipation effectively reducing ja and jb . esd caution
ad9148 rev. 0 | page 9 of 76 table 8. thermal resistance and maximum power pcb maximum power (w) package type t a (c) pcb layers pcb vias external heat sink 1 case t j (c) ja (c/w) 196-ball csp_bga 85 12 25 no csp_bga 125 18.0 2.22 196-ball csp_bga 85 12 25 yes csp_bga 125 16.0 2.50 196-ball bga_ed 85 12 25 no bga_ed 125 15.0 2.67 196-ball bga_ed 85 12 25 yes bga_ed 125 14.0 2.86 1 heat sink is used in the thermal model: 13 mm 13 mm, 15 mm tall. table 9. power vs. f dac rate and functionality maximum f dac (msps) 1 coarse modulation fine modulation (nco) maximum power (w) package heat-sink combination 2 pll off pll on pll off pll on 2.22 csp_bga no 820 740 695 630 2.50 csp_bga yes 950 875 810 740 2.67 bga_ep no 1000 945 870 810 2.86 bga_ep yes 1000 1000 940 870 1 typical maximum f dac rate with inverse sinc filter off. 2 heat sink is used in the ther mal model: 13 mm 13 mm, 15 mm tall.
ad9148 rev. 0 | page 10 of 76 pin configurations and function descriptions 1 23 4 5 67 8 9 10 11 12 13 14 1 23 4 5 67 8 9 10 11 12 13 14 a b c d e f g h j k l m n p a b c d e f g h j k l m n p avss cvdd18 + + + + avdd33 xx + x x xx x nc ref iout1 aux1 iout2 iout2 aux2 aux2 iout3 iout3 aux3 aux3 iout4 iout4 aux4 aux4 positive terminal negative terminal clk clk clk clk ref v ref i120 nc iout1 aux1 08910-004 figure 4. pin configuration (top view), analog and clock domain pins
ad9148 rev. 0 | page 11 of 76 1 23 4 5 67 8 9 10 11 12 13 14 1 23 4 5 67 8 9 10 11 12 13 14 a b c d e f g h j k l m n p a b c d e f g h j k l m n p x xxxxx x xxxxx + + sclk cs sdo sdio tms tck tdi tap interface tdo nc pll trch trch reset irq a0 a2 a0 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a9 a10 a11 a12 a13 a14 a15 a8 a9 a10 a11 a12 a13 a14 a15 a1 a1 b0 b2 b0 b2 b3 b3 b4 b4 b5 b5 b6 b6 b7 b7 b8 b9 b10 b11 b8 b9 b10 b11 b1 b1 b13 b13 b12 b14 b15 b12 b14 b15 fra fra frb frb dcib dcib dcia dcia dvss iovdd dvdd18 + x +lvds ?lvds a15 a15 08910-005 spi interface figure 5. pin configuration (top view), digital domain pins table 10. pin function description pin no. mnemonic description e6, e7, e8, e9 cvdd18 1.8 v clock supply. f5, f6, f7, f8, f9, f10 avdd33 3.3 v analog supply. a1, a2, a5, a10, a13, a14, b1, b2, b5, b10, b13, b14, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, e1, e2, e3, e4, e5, e10, e11, e12, e13, e14, f1, f2, f3, f4, f11, f12, f13, f14 avss analog supply ground. g5, g6, g7, g8, g9, g10, h5, h6, h7, h8, h9, h10 dvss digital supply ground. g3, g4 iovdd supply for serial ports (spi and tap), reset and irq . 1.8 v to 3.3 v can be supplied to these pins. j5, j6, j7, j8, j9, j10, k5, k6, k7, k8, k9, k10 dvdd18 1.8 v digital supply. b7, b8, h11 nc no connect. leave this pin unconnected. c1 iout1_n dac 1 complementary output current. d1 iout1_p dac 1 positive output current. a3 iout2_n dac 2 complementary output current. a4 iout2_p dac 2 positive output current. a11 iout3_p dac 3 positive output current. a12 iout3_n dac 3 complementary output current.
ad9148 rev. 0 | page 12 of 76 pin no. mnemonic description c14 iout4_n dac 4 complementary output current. d14 iout4_p dac 4 positive output current. c2 aux1_n auxiliary dac 1 complementary output current. d2 aux1_p auxiliary dac 1 positive output current. b3 aux2_n auxiliary dac 2 complementary output current. b4 aux2_p auxiliary dac 2 positive output current. b11 aux3_p auxiliary dac 3 positive output current. b12 aux3_n auxiliary dac 3 complementary output current. c13 aux4_n auxiliary dac 4 complementary output current. d13 aux4_p auxiliary dac 4 positive output current. a8 i120 tie to analog ground via a 10 k resistor to generate a 120 a reference current. a7 vref band gap voltage reference i/o. decouple to analog ground via a 0.1 f capacitor. output impedance is approximately 5 k. b6, a6 clk_p/clk_n positive/negative dac clock input (clk). b9, a9 refclk_p/refclk_n or sync_p/sync_n pll reference clock input (refclk_x). this pin has a secondary function as a synchronization input (sync_x). h4 irq active low open-drain interrupt requ est output. pull up to iovdd with a 10 k resistor. h3 reset an active low lvcmos input resets the device. pull up to iovdd. g1 sdo serial data output for spi. g2 cs active low chip select for spi. h1 sdio serial data input/output for spi. h2 sclk qualifying clock input for spi. g11, g12 trench connect this pin to vss. h12 pll_lock active high lvcmos output. it indicates the lock status of the pll circuitry. g13 tms tap test mode select g14 tdi tap test data input. h13 tck tap test clock input. h14 tdo tap test data output. m1, l1 a0_p/a0_n lvds data input pair, port a (lsb). p1, n1 a1_p/a1_n lvds data input pair, port a. m2, l2 a2_p/a2_n lvds data input pair, port a. p2, n2 a3_p/a3_n lvds data input pair, port a. p3, n3 a4_p/a4_n lvds data input pair, port a. p4, n4 a5_p/a5_n lvds data input pair, port a. p5, n5 a6_p/a6_n lvds data input pair, port a. p6, n6 a7_p/a7_n lvds data input pair, port a. p7, n7 a8_p/a8_n lvds data input pair, port a. p8, n8 a9_p/a9_n lvds data input pair, port a. p9, n9 a10_p/a10_n lvds data input pair, port a. p10, n10 a11_p/a11_n lvds data input pair, port a. p11, n11 a12_p/a12_n lvds data input pair, port a. p12, n12 a13_p/a13_n lvds data input pair, port a. p13, n13 a14_p/a14_n lvds data input pair, port a. p14, n14 a15_p/a15_n lvds data input pair, port a (msb). k13, j13 dcia_p/dcia_n lvds data clock input pair for port a. k14, j14 framea_p/framea_n lvds frame input for port a. k3, j3 b0_p/b0_n lvds data input pair, port b (lsb). m3, l3 b1_p/b1_n lvds data input pair, port b. k4, j4 b2_p/b2_n lvds data input pair, port b. m4, l4 b3_p/b3_n lvds data input pair, port b. m5, l5 b4_p/b4_n lvds data input pair, port b m6, l6 b5_p/b5_n lvds data input pair, port b. m7, l7 b6_p/b6_n lvds data input pair, port b.
ad9148 rev. 0 | page 13 of 76 pin no. mnemonic description m8, l8 b7_p/b7_n lvds data input pair, port b. m9, l9 b8_p/b8_n lvds data input pair, port b. m10, l10 b9_p/b9_n lvds data input pair, port b. m11, l11 b10_p/b10_n lvds data input pair, port b. k11, j11 b11_p/b11_n lvds data input pair, port b. m12, l12 b12_p/b12_n lvds data input pair, port b. k12, j12 b13_p/b13_n lvds data input pair, port b. m13, l13 b14_p/b14_n lvds data input pair, port b. m14, l14 b15_p/b15_n lvds data input pair, port b (msb). k2, j2 dcib_p/dcib_n lvds data clock input pair for port b. k1, j1 frameb_p/frameb_n lvds frame input for port b.
ad9148 rev. 0 | page 14 of 76 typical performance characteristics ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 spur level (dbc) f out (mhz) f data = 200msps, f data + f out f data = 310msps, f data + f out 08910-009 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 f out (mhz) harmonic level (dbc) f data = 200msps, second harmonic f data = 200msps, third harmonic f data = 310msps, second harmonic f data = 310msps, third harmonic 08910-006 figure 6. harmonic level vs. f out over f data , 2 interpolation, digital scale = 0 dbfs, full-scale current = 20 ma figure 9. highest digital spur vs. f out over f data , 2 interpolation, digital scale = 0 dbfs, full-scale current = 20 ma ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 f out (mhz) harmonic level (dbc) f data = 150msps, second harmonic f data = 150msps, third harmonic f data = 250msps, second harmonic f data = 250msps, third harmonic 0 50 100 150 200 250 300 350 400 450 500 08910-007 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 f out (mhz) spur level (dbc) f data = 150msps, f data + f out f data = 250msps, 2 f data ? f out 0 50 100 150 200 250 300 350 400 450 500 08910-010 figure 7. harmonic level vs. f out over f data , 4 interpolation, digital scale = 0 dbfs, full-scale current = 20 ma figure 10. highest digital spur vs. f out over f data , 4 interpolation, digital scale = 0 dbfs, full-scale current = 20 ma 0 50 100 150 200 250 300 350 400 450 500 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 f out (mhz) harmonic level (dbc) f data = 125msps, second harmonic f data = 125msps, third harmonic 08910-008 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 f out (mhz) spur level (dbc) f data = 125msps, f data + f out 0 50 100 150 200 250 300 350 400 450 500 08910-011 figure 8. harmonic level vs. f out , 8 interpolation over f data = 125 msps, digital scale = 0 dbfs, full-scale current = 20 ma figure 11. highest digital spur vs. f out , 8 interpolation, f data = 125 msps, digital scale = 0 dbfs, full-scale current = 20 ma
ad9148 rev. 0 | page 15 of 76 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 f out (mhz) harmonic level (dbc) 0dbfs, second harmonic ?6dbfs, second harmonic ?12dbfs, second harmonic ?18dbfs, second harmonic 08910-012 figure 12. second harmonic vs. f out over digital scale, full-scale current = 20 ma, 4 interpolation, f data = 150 msps ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 f out (mhz) harmonic level (dbc) 10ma, second harmonic 20ma, second harmonic 30ma, second harmonic 10ma, third harmonic 20ma, third harmonic 30ma, third harmonic 08910-013 figure 13. second harmonic vs. f out over full-scale current, digital scale = 0 dbfs, 4 interpolation, f data = 150 msps ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 power level (dbm) frequency (mhz) 08910-014 figure 14. 4 interpolation, f data = 150 msps, f out = 131 mhz ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 f out (mhz) harmonic level (dbc) 0dbfs, third harmonic ?6dbfs, third harmonic ?12dbfs, third harmonic ?18dbfs, third harmonic 08910-015 figure 15. third harmonic vs. f out over digital scale, full-scale current = 20 ma, 4 interpolation, f data = 150 msps ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 power level (dbm) frequency (mhz) 08910-016 figure 16. 2 interpolation, f data = 310 msps, f out = 131 mhz ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 power level (dbm) frequency (mhz) 08910-017 figure 17. 8 interpolation, f data = 125 msps, f out = 131 mhz
ad9148 rev. 0 | page 16 of 76 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 350 imd (dbc) f out (mhz) f data = 200msps f data = 310msps 08910-018 figure 18. imd vs. f out over f data , 2 interpolation, digital scale = 0 dbfs, full-scale current = 20 ma ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 350 400 450 500 f out (mhz) imd (dbc) f data = 125msps 08910-019 figure 19. imd vs. f out , 8 interpolation, f data = 125 msps, digital scale = 0 dbfs, full-scale current = 20 ma ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 f out (mhz) imd (dbc) 0dbfs ?6dbfs ?12dbfs ?18dbfs 08910-020 figure 20. imd vs. f out over digital scale, 4 interpolation, f data = 150 msps, full-scale current = 20 ma ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 0 50 100 150 200 250 300 350 400 450 500 f out (mhz) imd (dbc) f data = 150msps f data = 250msps 08910-021 figure 21. imd vs. f out over f data , 4 interpolation, digital scale = 0 dbfs, full-scale current = 20 ma ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 f out (mhz) imd (dbc) 10ma 20ma 30ma 0 50 100 150 200 250 300 08910-022 figure 22. imd vs. f out over full-scale current, 4 interpolation, f data = 150 msps, digital scale = 0 dbfs ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 f out (mhz) imd (dbc) 0 50 100 150 200 250 300 pll off pll on 08910-023 figure 23. imd vs. f out , pll on and off, digital scale = 0 dbfs, full-scale current = 20 ma
ad9148 rev. 0 | page 17 of 76 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ? 144 0 50 100 150 200 250 300 350 400 nsd (dbm/hz) f out (mhz) 1, 200msps 2, 200msps 4, 200msps 8, 100msps 08910-024 figure 24. single-tone nsd performance vs. f out , digital scale = 0 dbfs, 4 f data = 200 msps, full-scale current = 20 ma ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ? 144 0 50 100 150 200 250 300 350 400 nsd (dbm/hz) f out (mhz) 2, 200msps 4, 200msps 8, 100msps 08910-025 figure 25. single-tone nsd performance vs. f out , digital scale = 0 dbfs, 4 f data = 200 msps, full-scale current = 20 ma, pll on ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ? 144 0 50 100 150 200 250 300 350 400 nsd (dbm/hz) f out (mhz) 0db ?6db ?12db ?18db 08910-026 figure 26. single-tone nsd performance vs. f out over digital scale, 4 f data = 200 msps, full-scale current = 20 ma ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ? 144 0 50 100 150 200 250 300 350 400 nsd (dbm/hz) f out (mhz) 1, 200msps 2, 200msps 4, 200msps 8, 100msps 08910-027 figure 27. eight-tone nsd performance vs. f out , digital scale = 0 dbfs, full-scale current = 20 ma ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ? 144 0 50 100 150 200 250 300 350 400 nsd (dbm/hz) f out (mhz) 2, 200msps 4, 200msps 8, 100msps 08910-028 figure 28. single-tone nsd performance vs. f out , digital scale = 0 dbfs, full-scale current = 20 ma, pll on ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ? 144 0 50 100 150 200 250 300 350 400 nsd (dbm/hz) f out (mhz) 0db ?6db ?12db ?18db 08910-029 figure 29. eight-tone nsd performance vs. f out over digital scale, 4 f data = 200 msps, full-scale current = 20 ma
ad9148 rev. 0 | page 18 of 76 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 50 100 150 200 250 300 350 aclr (dbc) 0db, pll on 0db, pll off ?3db, pll off ?6db, pll off f out (mhz) 08910-030 figure 30. one-carrie r w-cdma aclr vs. f out , adjacent channel, 4 interpolation, f data = 184.32 mhz ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 50 100 150 200 250 300 350 aclr (dbc) 0db, pll on 0db, pll off ?3db, pll off ?6db, pll off f out (mhz) 08910-031 figure 31. one-carrie r w-cdma aclr vs. f out , alternate channel, 4 interpolation, f data = 184.32 mhz ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 50 100 150 200 250 300 350 aclr (dbc) 0db, pll on 0db, pll off ?3db, pll off ?6db, pll off f out (mhz) 08910-032 figure 32. one-carrie r w-cdma aclr vs. f out , second alternate channel, 4 interpolation, f data = 184.32 mhz center 150.00mhz vbw 300khz span 34.68mhz #res bw 30khz rms results freq offset ref bw lower dbc dbm upper dbc dbm c arrier power 5.000mhz 3.840mhz ?78.88 ?92.35 ?77.98 ?91.45 ? 13.47dbm/ 10.00mhz 3.840mhz ?82.12 ?95.59 ?82.65 ?96.12 3 .84000mhz 15.00mhz 3.840mhz ?82.18 ?95.65 ?82.28 ?95.75 sweep 112.5ms (601 pts) 08910-033 figure 33. one-carr ier w-cdma aclr, f out = 150 mhz, 4 interpolation, f data = 184.32 mhz, pll off center 150.00mhz vbw 300khz span 34.68mhz #res bw 30khz rms results freq offset ref bw lower dbc dbm upper dbc dbm c arrier power 5.000mhz 3.840mhz ?74.50 ?87.27 ?73.79 ?86.56 ? 12.77dbm/ 10.00mhz 3.840mhz ?82.72 ?95.49 ?82.99 ?95.76 3 .84000mhz 15.00mhz 3.840mhz ?82.97 ?95.74 ?83.54 ?96.31 sweep 112.5ms (601 pts) 08910-034 figure 34. one-carr ier w-cdma aclr, f out = 150 mhz, 4 interpolation, f data = 184.32 mhz, pll on start 1.0mhz vbw 30khz stop 368.6mhz #res bw 30khz sweep 1.685s (601 pts) 08910-035 figure 35. one-carrier w-cdma, f out = 150 mhz, f dac = 737.28 msps, 4 interpolation, ?3 dbfs
ad9148 rev. 0 | page 19 of 76 center 150.00mhz vbw 300khz span 59.58mhz #res bw 30khz total carrier power ?13.30dbm/15.3 600mhz ref carrier power ?19.14dbm/3.84 000mhz rcc filter: on filter alpha 0.22 1 ?19.14dbm freq offset integ bw lower dbc dbm upper dbc dbm 2 ?19.29dbm 5.000mhz 3.840mhz ?72.59 ?91.81 ?72.99 ?92.22 3 ?19.24dbm 10.00mhz 3.840mhz ?73.58 ?92.81 ?74.45 ?93.67 4 ?19.61dbm 15.00mhz 3.840mhz ?75.18 ?94.40 ?75.28 ?94.51 sweep 193.2ms (601 pts) 0 8910-036 start 1.0mhz vbw 30khz stop 368.6mhz #res bw 30khz sweep 1.685s (601 pts) 08910-038 figure 38. four-carrier w-cdma, f out = 150 mhz, f dac = 737.28 msps, 4 interpolation, ?3 dbfs figure 36. four-carrier w-cdma, f out = 150 mhz, f dac = 737.28 msps, 4 interpolation, ?3 dbfs, pll off center 150.00mhz vbw 300khz span 59.58mhz #res bw 30khz total carrier power ?13.28dbm/15.3 600mhz ref carrier power ?19.07dbm/3.84 000mhz rcc filter: on filter alpha 0.22 1 ?19.07dbm freq offset integ bw lower dbc dbm upper dbc dbm 2 ?19.42dbm 5.000mhz 3.840mhz ?64.50 ?64.39 ?83.56 3 ?19.28dbm 10.00mhz 3.840mhz ?65.12 ?65.20 ?84.37 4 ?19.45dbm 15.00mhz 3.840mhz ?65.40 ?83.67 ?84.29 ?84.57 ?65.35 ?84.52 sweep 193.2ms (601 pts) 0 8910-037 ?110 ?108 ?106 ?104 ?102 ?100 ?98 ?96 ?94 ?92 ?90 ?88 ?86 ?84 ?82 ? 80 0 50 100 150 200 250 300 crosstalk (db) f out (mhz) 08910-039 figure 39. crosstalk (dac set 1 to dac set 2), 4 interpolation, f data = 150 msps, digital scale = 0 dbfs, full-scale current = 20 ma figure 37. four-carrier w-cdma, f out = 150 mhz, f dac = 737.28 msps, 4 interpolation, ?3 dbfs, pll on
ad9148 rev. 0 | page 20 of 76 terminology integral nonlinearity (inl) inl is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for ioutx_p, 0 ma output is expected when the inputs are all 0s. for ioutx_n, 0 ma output is expected when all inputs are set to 1. gain error the difference between the actual and ideal output span. the actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degrees celsius. for reference drift, the drift is reported in ppm per degrees celsius. power supply rejection (psr) the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. in-band spurious free dynamic range (sfdr) the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. out-of-band spurious free dynamic range (sfdr) the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the nyquist frequency of the dac output sample rate. normally, energy in this band is rejected by the interpolation filters. this specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the dac output. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. interpolation filter an interpolation filter up-samples the input digital data by a multiple of f data (interpolation rate) and then filters out the undesired spectral images created by the up-sampling process. adjacent channel leakage ratio (aclr) the ratio in dbc between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two-part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected.
ad9148 rev. 0 | page 21 of 76 serial peripheral interface sdo spi port sdio s clk cs g1 h1 g2 h2 08910-040 figure 40. spi por t the serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro- controllers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi and intel ? ssr protocols. the interface allows read/write access to all registers that configure the ad9148. single- or multiple-byte transfers are supported, as well as msb- first or lsb-first transfer formats. the serial interface ports can be configured as a single pin i/o (sdio) or two unidirectional pins for input/output (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the ad9148. phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight sclk rising edges. the instruction byte provides the serial port controller with information regarding the data transfer cycle, phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is a read or a write, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the device. a logic high on the cs pin followed by a logic low resets the spi port timing to the initial state of the instruction cycle. from this state, the next eight rising sclk edges represent the instruction bits of the current i/o operation, regardless of the state of the internal registers or the other signal levels at the inputs to the spi port. if the spi port is in an instruction cycle or a data transfer cycle, none of the present data is written. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycle is a transfer of one or more data bytes. registers change immediately upon writing to the last bit of each transfer byte. data format the instruction byte contains the information shown in table 11 . table 11. spi instruction byte i7 (msb) i6 i5 i4 i3 i2 i1 i0 (lsb) r/ w a6 a5 a4 a3 a2 a1 a0 r/ w , bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. logic high indicates a read operation, and logic 0 indicates a write operation. a6 through a0, bit 6 through bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the device based on the lsb-first bit (register 0x00, bit 6). spi pin descriptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and runs the internal state machines. the maximum frequency of sclk is 40 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select ( cs ) active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the sdo and sdio pins go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. serial data i/o (sdio) data is always written into the device on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by register 0x00, bit 7. the default is logic 0, configuring the sdio pin as unidirectional. serial data output (sdo) data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the device operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state.
ad9148 rev. 0 | page 22 of 76 spi options the serial port can support both msb-first and lsb-first data formats. this functionality is controlled by the lsb first bit (register 0x00, bit 6). the default is msb first (lsb first = 0). when lsb first = 0 (msb first), the instruction and data bit must be written from msb to lsb. multibyte data transfers in msb- first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow from the high address to the low address. in msb- first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. when lsb first = 1 (lsb first), the instruction and data bit must be written from lsb to msb. multibyte data transfers in lsb- first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. the serial port controller data address decrements from the data address written toward 0x00 for multibyte i/o operations if the msb-first mode is active. the serial port controller address increments from the data address written toward 0x1f for multibyte i/o operations if the lsb-first mode is active. r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle scl k sdio sdo 08910-041 cs figure 41. serial register interface timing msb first a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle sclk sdio sdo 08910-042 cs figure 42. serial register interface timing lsb first instruction bit 6 instruction bit 7 s clk sdio t ds t dcsb t dh t pwh t pwl t sclk 08910-043 cs figure 43. timing diagram for spi register write data bit n ? 1 data bit n sclk sdio sdo t dv 08910-044 cs figure 44. timing diagram for spi register read
ad9148 rev. 0 | page 23 of 76 spi register map table 12. register map addr register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0x00 comm sdio direction lsb/ msb first software reset dac spi select 0x00 0x01 power control power- down dac set 1 power- down dac set 2 power- down data receiver 0x00 0x03 data format binary format q first enable dual-port mode bus swap byte mode byte swap 0x20 0x04 interrupt enable 0 enable pll lock lost enable pll lock enable sync lock lost enable sync lock enable fifo spi aligned enable fifo warning 1 enable fifo warning 2 0x00 0x05 interrupt enable 1 enable aed compare pass enable aed compare fail enable sed compare fail 0x00 0x06 event flag 0 pll lock lost pll lock sync lock lost sync lock fifo spi aligned fifo warning 1 fifo warning 2 0x07 event flag 1 aed compare pass aed compare fail sed compare fail 0x08 clock receiver control clk duty correction refclk duty correction clk cross correction refclk cross correction 0 1 1 1 0x37 0x0a pll control 0 pll enable pll manual enable manual vco band[5:0] 0x40 0x0c pll control 1 pll loop bandwidth[2:0] 0 1 0 0 1 0xf1 0x0d pll control 2 n2[1:0] pll cross control enable n0[1:0] n1[1 :0] 0xd9 0x0e pll status 0 pll control voltage[3:0] 0x0f pll status 1 vco band readback[5:0] 0x10 sync control 0 sync enable fifo rate/ data rate toggle rising edge sync sync averaging[2:0] 0x08 0x11 sync control 1 sync phase request[5:0] 0x00 0x12 sync status 0 sync lost sync locked 0x14 data receiver control one dci 0x00 0x15 data receiver status lvds rcvr frame high lvds rcvr frame low lvds rcvr dci high lvds rcvr dci low lvds rcvr port b high lvds rcvr port b low lvds rcvr port a high lvds rcvr port a low 0x17 fifo status/ control port a fifo warning 1 fifo warning 2 fifo reset aligned fifo spi align ack fifo spi align requesting fifo phase offset[2:0] 0x00 0x18 fifo status port a fifo level[7:0] 0x19 fifo status/ control port b fifo warning 1 fifo warning 2 fifo reset aligned fifo spi align ack fifo spi align requesting fifo phase offset[2:0] 0x00 0x1a fifo status port b fifo level[7:0] 0x1c hb1 control enable pre mod bypass sinc ?1 hb1[1:0] bypass hb1 0x40 0x1d hb2 control hb2[2:0] bypass hb2 0x00 0x1e hb3 control bypass phase adj hb3[2:0] bypass hb3 0x81 0x1f chip id chip id[7:0] 0x20
ad9148 rev. 0 | page 24 of 76 addr register name bit 7 bit 6 bit 5 bit 4 bi t 3 bit 2 bit 1 bit 0 default 0x20 1 coeff i byte 0 0 coeff_1i[3:0] coeff_0i[2:0] 0x00 0x21 1 coeff i byte 1 coeff_3i[2:0] coeff_2i[4:0] 0xc0 0x22 1 coeff i byte 2 coeff_4i[2:0] 0 coeff_3i[6:3] 0xef 0x23 1 coeff i byte 3 0 coeff_4i[9:3] 0x7f 0x24 1 coeff q byte 0 0 coeff_1q[3:0] coeff_0q[2:0] 0x69 0x25 1 coeff q byte 1 coeff_3q[2:0] coeff_2q[4:0] 0xe6 0x26 1 coeff q byte 2 coeff_4q[2:0] 0 coeff_3q[6:3] 0x0d 0x27 1 coeff q byte 3 0 coeff_4q[9:3] 0x00 0x28 1 i phase adj lsb phase word i[7:0] 0x00 0x29 1 i phase adj msb phase word i[9:8] 0x00 0x2a 1 q phase adj lsb phase word q[7:0] 0x00 0x2b 1 q phase adj msb phase word q[9:8] 0x00 0x2c 1 i dc offset lsb dc offset i[7:0] 0x00 0x2d 1 i dc offset msb dc offset i[15:8] 0x00 0x2e 1 q dc offset lsb dc offset q[7:0] 0x00 0x2f 1 q dc offset msb dc offset q[15:8] 0x00 0x30 1 idac fsc adj idac fsc adj[7:0] 0xf9 0x31 1 idac control idac sleep idac fsc adj[9:8] 0x01 0x32 1 aux idac data aux idac data[7:0] 0x00 0x33 1 aux idac control aux idac sign aux idac current direction aux idac power- down aux idac data[9:8] 0x00 0x34 1 qdac fsc adj qdac fsc adj[7:0] 0xf9 0x35 1 qdac control qdac sleep qdac fsc adj[9:8] 0x01 0x36 1 aux qdac data aux qdac data[7:0] 0x00 0x37 1 aux qdac control aux qdac sign aux qdac current direction aux qdac power- down aux qdac data[9:8] 0x00 0x38 1 sed_s0_l sed compare pattern sample0[7:0] 0xb6 0x39 1 sed_s0_h sed compare pattern sample0[15:8] 0x7a 0x3a 1 sed_s1_l sed compare pattern sample1[7:0] 0x45 0x3b 1 sed_s1_h sed compare pattern sample1[15:8] 0xea 0x3c 1 sed3_s2_l sed compare pattern sample2[7:0] 0x16 0x3d 1 sed3_s2_h sed compare pattern sample2[15:8] 0x1a 0x3e 1 sed4_s3_l sed compare pattern sample3[7:0] 0xc6 0x3f 1 sed4_s3_h sed compare pattern sample3[15:8] 0xaa 0x40 sed control/ status sed compare enable port b error detected port a error detected auto- clear enable port b compare failed port a compare failed compare passed 0x00 0x41 1 sed_r_l sed status rising edge samples[7:0] 0x42 1 sed_r_h sed status rising edge samples[15:8] 0x43 1 sed_f_l sed status falling edge samples[7:0] 0x44 1 sed_f_h sed status falling edge samples[15:8] 0x50 1 i gain control i gain[7:0] 0x40 0x51 1 q gain control q gain[7:0] 0x40
ad9148 rev. 0 | page 25 of 76 addr register name bit 7 bit 6 bit 5 bit 4 bi t 3 bit 2 bit 1 bit 0 default 0x54 ftw (lsb) ftw[7:0] 0x00 0x55 ftw ftw [15:8] 0x00 0x56 ftw ftw[23:16] 0x00 0x57 ftw (msb) ftw[31:24] 0x00 0x58 phase offset (msb) nco phase offset[15:8] 0x00 0x59 phase offset (lsb) nco phase offset[7:0] 0x00 0x5a dds/mod control bypass dds/mod frame nco reset ack frame nco reset request ftw update ack ftw update request sideband select 0x80 0x5c die temp control 0 latch temp data temp sensor power-down 0x01 0x5d die temp control 1 0 0 0 0 1 0 1 0 0x20 0x5e die temp lsb die temp[7:0] 0x5f die temp msb die temp[15:8] 0x72 dci delay dci delay[1:0] 0x00 0x74 lvds pad ctrl lvds input resistance[3:0] 0x0d 1 register 0x20 to register 0x3f and regi ster 0x41 to register 0x51 configure dac 1 (i) and dac 2 (q) data paths with dac spi se lect = 0 (register 0x00[4]). register 0x20 to register 0x3f and register 0x41 to register 0x51 configure dac 3 (i) and dac 4 (q) data path s with dac spi select = 1 (regis ter 0x00[4]). spi register descriptions table 13. register descriptions register name addr (hex) bit name function default comm 00 7 sdio sdio operation. 0 0 = sdio operates as an input only. 1 = sdio operates as bidirectional input/output. 6 lsb/msb first spi communication lsb first (default is msb first). 0 0 = msb first. 1 = lsb first. 5 software reset software reset. 0 reset is asserted when this bit transitions from 0 to 1. 4 dac spi select selects which dac data path register 0x20 to register 0x3f and register 0x41 to register 0x51 configure. 0 0 = dac 1 (i path) and dac 2 (q path) are configured. 0 1 = dac 3 (i path) and dac 4 (q path) are configured. power control 01 7 power-down dac set 1 power down dac 1 and power down dac 2. 0 6 power-down dac set 2 power down dac 3 and power down dac 4. 0 5 power-down data receiver power down the input data receiver. 0
ad9148 rev. 0 | page 26 of 76 register name addr (hex) bit name function default data format 03 7 binary format input data is in twos comple ment format (0) or unsigned binary format (1). 0 6 q first enable indicates i/q data pairing on data input; i first (0), q first (1). 0 5 dual-port mode number of input data ports used. 1 single port (0), dual port (1). 4 bus swap 0 = normal data input bus pin out (msb to lsb). 0 1 = inverted data input bus pin out (lsb to msb). 3 byte mode 0 = data input bu s is 16-bit wide on each port. 0 1 = data input bus is two 8-bit wide buses on port a. 2 byte swap 0 = normal data input bus pin out (msb to lsb). 0 1 = inverted data input bus pin out (lsb to msb). interrupt enable 0 04 7 enable pll lock lost enables interrupt for pll lock lost. 0 6 enable pll lock enables interrupt for pll lock. 0 5 enable sync lock lost enables interrupt for sync lock lost. 0 4 enable sync lock enables interrupt for sync lock. 0 2 enable fifo spi aligned enables interrupt for fifo spi aligned. 0 1 enable fifo warning 1 enables interrupt for fifo warning 1. 0 0 enable fifo warning 2 enables interrupt for fifo warning 2. 0 interrupt enable 1 05 4 enable aed compare pass enables interrupt for aed compare pass. 0 3 enable aed compare fail enables interrupt for aed compare fail. 0 2 enable sed compare fail enables interrupt for sed compare fail. 0
ad9148 rev. 0 | page 27 of 76 register name addr (hex) bit name function default event flag 0 (all bits are high when interrupt is active. clear interrupt by writing respective bit high.) 06 7 pll lock lost 1 = indicates that the pll that was previously locked has unlocked from the reference signal. 0 6 pll lock 1 = indicates that the pll has locked to the reference clock input. 0 5 sync lock lost 1 = indicates that the sync logic that was previously locked has lost alignment. 0 4 sync lock 1 = indicates that the sync logic achieved sync alignment. this is indicated when no phase changes are requested for at least a few full averaging cycles. 0 2 fifo spi aligned 1 = indicates that a fifo reset originating from a serial port- based request has successfully completed. 0 1 fifo warning 1 1 = indicates that the difference between the fifo read and write pointers is 1. 0 0 fifo warning 2 1 = indicates that the difference between the fifo read and write pointers is 2. 0 event flag 1(all bits are high when interrupt is active. clear interrupt by writing respective bit high). 07 4 aed compare pass 1 = indicates that the sed logic detected a valid input data pattern comparison against the preprogrammed expected values. 0 3 aed compare fail 1 = indicates that the sed logic detected an invalid input data pattern comparison against the preprogrammed expected values. this automatically clea rs when eight valid i/q data pairs are received. 0 2 sed compare fail 1 = indicates that the sed logic detected an invalid input data pattern comparison against the preprogrammed expected values. 0 clock receiver control 08 7 clk duty correction enables duty-cycle correction on clk input. 0 6 refclk duty correction enables duty-cycle correction on refclk input. 0 5 clk cross correction enables differential crossing correction on clk input. 1 4 refclk cross correction enables differential crossing co rrection on refclk input. 1 3:0 0111 always set these bits to 0111 0111 pll control 0 0a 7 pll enable en ables pll clock multiplier. 0 6 pll manual enable enables pll band selection mode (0 = auto, and 1 = manual). 1 5:0 manual vco band vco band used in manual mode. 0 pll control 1 0c 7:5 pll loop bandwidth selects pll loop filter bandwidth. 110 000 = narrowest bandwidth. 111 = widest bandwidth. 4:0 01001 set these bits to 01001 for optimal pll operation. 10001
ad9148 rev. 0 | page 28 of 76 register name addr (hex) bit name function default pll control 2 0d 7:6 n2 dacclk to pll controller clock rate (f pc_clk ). 11 00 = 2. 01 = 4. 10 = 8. 11 = 16. f pc_clk must always be less than 50 mhz. 4 pll cross control enable enables pll cross-point control. 3:2 n0 vco-to-dacclk divider. 001 00 = 1. 01 = 2. 10 = 4. 11 = 4. 1:0 n1 dacclk-to-refclk divider. 01 00 = 2. 01 = 4. 10 = 8. 11 = 16. pll status 0 0e 3:0 pll control voltage pll vco control voltage readback value. read- only pll status 1 0f 5:0 vco band readback vco band value. read- only sync control 0 10 7 sync enable enables synchronization logic. 0 6 fifo rate/data rate toggle operates synchronization at the fifo reset rate (0)/data rate (1). 0 3 rising edge sync rising edge of clk samples sync input (1), falling edge of clk samples sync input (0). 1 2:0 sync averaging average sync input of number of samples. 000 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128.
ad9148 rev. 0 | page 29 of 76 register name addr (hex) bit name function default sync control 1 11 5:0 sync phase request offset of internal divided by 64 clock phase after sync. 000000 000000 = 0 dac clocks. 111111 = 63 dac clocks. sync status 0 12 7 sync lost synchronization lost. read- only 6 sync locked synchronization found. read- only data receiver control 14 6 one dci 0 = two dcis used, dcia_x and dcib_x. 0 1 = one dci used, dcia_x. data receiver status 15 7 lvds receiver frame high frame input lvds level > 1.7 v. read- only 6 lvds receiver frame low frame input lvds level < 0.7 v. read- only 5 lvds receiver dci high dci input lvds level > 1.7 v. read- only 4 lvds receiver dci low dci input lvds level < 0.7 v. read- only 3 lvds receiver port b high port b input lvds level > 1.7 v. read- only 2 lvds receiver port b low port b input lvds level < 0.7 v. read- only 1 lvds receiver port a high port a input lvds level > 1.7 v. read- only 0 lvds receiver port a low port a input lvds level < 0.7 v. read- only fifo status/ control port a 17 7 fifo warning 1 fifo read and write pointers within 1. read- only 6 fifo warning 2 fifo read and write pointers within 2 read- only 5 fifo reset aligned fifo read and write pointers aligned after chip reset. read- only 4 fifo spi align acknowledge fifo read and write pointers aligned after spi driven fifo reset. read- only 3 fifo spi align requesting request fifo read and write pointers alignment via spi. 0 2:0 fifo phase offset fifo read and write pointer phase offset from optimal phase following fifo reset. 000 000 = 0 offset from optimal phase. 111 = 7 offset from optimal phase. the optimal value is 0.
ad9148 rev. 0 | page 30 of 76 register name addr (hex) bit name function default fifo status port a 18 7:0 fifo level thermo meter encoded measure of the fifo level. read- only fifo status/ control port b 19 7 fifo warning 1 fifo read and write pointers within 1. read- only 6 fifo warning 2 fifo read and write pointers within 2. read- only 5 fifo reset aligned fifo read and write pointers aligned after chip reset. read- only 4 fifo spi align acknowledge fifo read and write pointers aligned after spi driven fifo reset. read- only 3 fifo spi align requesting request fifo read and write pointers alignment via spi. 0 2:0 fifo phase offset fifo read and write pointer phase offset from optimal phase following fifo reset. 000 000 = 0 offset from optimal phase. 111 = 7 offset from optimal phase. the optimal value is 0. fifo status port b 1a 7:0 fifo level ther mometer encoded measure of the fifo level. read- only hb1 control 1c 7 enable pre mod enable fs/2 modulation stage that precedes stage 1 interpolation filter. 0 6 bypass sinc-1 sinc-1 filter bypass. 1 2:1 hb1[1:0] modulation mode for first stage interpolation filter (f hb1 = 2 f in1 ). 00 00 = input signal modulated by dc. filter pass band is from ?0.2 to +0.2 of f hb1 . 01 = input signal modulated by dc. filter pass band is from 0.05 to 0.45 of f hb1 . 10 = input signal modulated by f hb1 /2. filter pass band is from 0.3 to 0.7 of f hb1 . 11 = input signal modulated by f hb1 /2. filter pass band is from 0.55 to 0.95 of f hb1 . 0 bypass hb1 first stage interpolation filter bypass. 0
ad9148 rev. 0 | page 31 of 76 register name addr (hex) bit name function default hb2 control 1d hb2[2:0] modulation mode for second stage interpolation filter (f hb2 = 2 f in2 ). 000 000 = input signal modulated by dc. filter pass band is from ?0.1 to +0.1 of f hb2 . 001 = input signal modulated by dc. filter pass band is from 0.025 to 0.225 of f hb2 . 010 = input signal modulated by f hb2 /4. filter pass band is from 0.15 to 0.35 of f hb2 . 011 = input signal modulated by f hb2 /4. filter pass band is from 0.275 to 0.475 of f hb2 . 100 = input signal modulated by f hb2 /2. filter pass band is from 0.4 to 0.6 of f hb2 . 101 = input signal modulated by f hb2 /2. filter pass band is from 0.525 to 0.725 of f hb2 . 110 = input signal modulated by 3 f hb2 /4. filter pass band is from 0.65 to 0.85 of fhb2. 111 = input signal modulated by 3 f hb2 /4. filter pass band is from 0.775 to 0.975 of f hb2 . 0 bypass hb2 second stage interpolation filter bypass. 0 hb3 control 1e 7 bypass phase adj 1 = bypass phase compensation. 1 3:1 hb3[2:0] modulation mode for third stage interpolation filter (f hb3 = 2 f in3 ). 000 000 = input signal modulated by dc. filter pass band is from ?0.1 to +0.1 of f hb3 . 001 = input signal modulated by dc. filter pass band is from 0.025 to 0.225 of f hb3 . 010 = input signal modulated by f hb3 /4. filter pass band is from 0.15 to 0.35 of f hb3 . 011 = input signal modulated by f hb3 /4. filter pass band is from 0.275 to 0.475 of f hb3 . 100 = input signal modulated by f hb3 /2. filter pass band is from 0.4 to 0.6 of f hb3 . 101: input signal modulated by f hb3 /2. filter pass band is from 0.525 to 0.725 of f hb3 . 110 = input signal modulated by 3 f hb3 /4. filter pass band is from 0.65 to 0.85 of f hb3 . 111 = input signal modulated by 3 f hb3 /4. filter pass band is from 0.775 to 0.975 of f hb3 . 0 bypass hb3 third stage interpolation filter bypass. 1 chip id 1f 7:0 chip id chip id readback. 20
ad9148 rev. 0 | page 32 of 76 register name addr (hex) bit name function default coeff i byte 0 20 7 0 set this bit to 0. 0 6:3 coeff_1i[3:0] i-path dac sinc -1 filter coefficient 2 in twos complement format. 0 2:0 coeff_0i i-path dac sinc -1 filter coefficient 1 in twos complement format. 0 set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. coeff i byte 1 21 7:5 coeff_3i[2:0] i-path dac sinc -1 filter coefficient 4 (lsb) in twos complement format. 6 4:0 coeff_2i i-path dac sinc -1 filter coefficient 3 in twos complement format. 0 set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. coeff i byte 2 22 7:5 coeff_4i[2:0] i-path dac sinc -1 filter coefficient 5 (lsb) in twos complement format. 7 4 0 set this bit to 0. 0 3:0 coeff_3i[6:3] set i-path dac sinc -1 filter coefficient 4 (msb) in twos complement format. f dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. coeff i byte 3 23 7 0 set this bit to 0. 0 6:0 coeff_4i[9:3] i-path dac sinc -1 filter coefficient 5 (msb) in twos complement format. 7f set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. coeff q byte 0 24 7 0 set this bit to 0. 0 6:3 coeff_1q[3:0] q-path dac sinc -1 filter coefficient 2 in twos complement format. d 2:0 coeff_0q q-path dac sinc -1 filter coefficient 1 in twos complement format. 1 set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path. coeff q byte 1 25 7:5 coeff_3q[2:0] q-path dac sinc -1 filter coefficient 4 (lsb) in twos complement format. 7 4:0 coeff_2q q-path dac sinc -1 filter coefficient 3 in twos complement format. 6 set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path.
ad9148 rev. 0 | page 33 of 76 register name addr (hex) bit name function default coeff q byte 2 26 7:5 coeff_4q[2:0] q-path dac sinc -1 filter coefficient 5 (lsb) in twos complement format. 0 4 0 set this bit to 0. 0 3:0 coeff_3q[6:3] q-path dac sinc -1 filter coefficient 4 (msb) in twos complement format. d set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path. coeff q byte 3 27 7 0 set this bit to 0. 0 6:0 coeff_4q[9:3] q-path dac sinc -1 filter coefficient 5 (msb) in twos complement format. 0 set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path. i phase adj lsb 28 7:0 phase word i[7:0] see register 0x29. 0 i phase adj msb 29 1:0 phase word i[9:8] phase word i[9:0] is used to insert a phase offset between the i and q data paths. the adjustment range is 1.75. 0 set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. q phase adj lsb 2a 7:0 phase word q[7:0] see register 0x2b. 0 q phase adj msb 2b 1:0 phase word q[9:8] phase word q[9:0] is used to insert a phase offset between the i and q data paths. the adjustment range is 1.75. 0 set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path. i dc offset lsb 2c 7:0 dc offset i[7:0] see register 0x2d. 0 i dc offset msb 2d 7:0 dc offset i[15:8] dc offset i[15:0] is a value added directly to the samples written to the idac. the lsb bit weight is 2 0 . the adjustment range is 10 ma. set dac spi select = 0 to configure dac 1 path. 0 set dac spi select = 1 to configure dac 3 path. q dc offset lsb 2e 7:0 dc offset q[7:0] see register 0x2f. 0 q dc offset msb 2f 7:0 dc offset q[15:8] dc offset q[15:0] is a value added directly to the samples written to the qdac. the lsb bit weight is 2 0 . the adjustment range is 10 ma. set dac spi select = 0 to configure dac 2 path. 0 set dac spi select = 1 to configure dac 4 path. 0
ad9148 rev. 0 | page 34 of 76 register name addr (hex) bit name function default idac fsc adj 30 7:0 idac fsc adj idac full-scale current adjustment (lsb part). idac fs adj[9:0] sets the full-scale current of the idac. the full-scale current can be adjusted from 8.64 ma to 31.6 ma in step sizes of approximately 22.5 a. f9 0x000 = 8.64 ma. ... 0x200 = 20.14 ma. 0x3ff = 31.66 ma. set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. idac control 31 7 idac sleep i dac sleep mode (fast wake-up mode). 0 1:0 idac fsc adj[9:8] idac full-scale current adjustment (msb part) 01 set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. aux idac data 32 7:0 aux idac data auxiliary idac data (lsb part). aux idac data[9:0] sets the magnitude of the aux dac current. the range is 0 ma to 2 ma, and the step size is 2 a. 00 0x000 = 0.000 ma. 0x001 = 0x002 ma. 0x3ff = 2.046 ma. set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. aux idac control 33 7 aux idac sign auxiliary idac output sign. 0 0 = positive, current is directed to the auxx_p pin. 1 = negative, current is directed to the auxx_n pin. 6 aux idac current direction auxiliary idac current direction. 0 0 = source. 1 = sink. 5 aux idac power-down auxiliary idac power-down. 0 1:0 aux idac data[9:8] auxiliary idac data (msb part). 00 set dac spi select = 0 to configure dac 1 path. set dac spi select =1 to configure dac 3 path.
ad9148 rev. 0 | page 35 of 76 register name addr (hex) bit name function default qdac fsc adj 34 7:0 qdac fsc adj q dac full-scale current adjustment (lsb part). qdac fs adj[9:0] sets the full-scale current of the qdac. the full-scale current can be adjusted from 8.64 ma to 31.6 ma in step sizes of approximately 22.5 a. f9 0x000 = 8.64 ma ... 0x200 = 20.14ma 0x3ff = 31.66 ma set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path. qdac control 35 7 qdac sleep q dac sleep mode (fast wake-up mode). 0 1:0 qdac fsc adj[9:8] qdac full-scale current adjustment (msb part). 01 set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path. aux qdac data 36 7:0 aux qdac data auxiliary qdac data (lsb part). aux qdac data[9:0] sets the magnitude of the aux dac current. the range is 0 ma to 2 ma, and the step size is 2 a. 00 0x000 = 0.000 ma. 0x001 = 0x002 ma. 0x3ff = 2.046 ma. set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path. aux qdac control 37 7 aux qdac sign auxiliary qdac output sign. 0 0 = positive, current is directed to the auxx_p pin. 1 = negative, current is directed to the auxx_n pin. 6 aux qdac current direction auxiliary qdac current direction. 0 0 = source. 1 = sink. 5 aux qdac power-down auxiliary qdac power-down. 0 1:0 aux qdac data[9:8] auxiliary qdac data (msb part). 00 set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path.
ad9148 rev. 0 | page 36 of 76 register name addr (hex) bit name function default sed_s0_l 38 7:0 sed compare pattern sample0[7:0] compare pattern sample0[15:0] is the word that is compared with data sample 0 captured at the input interface by the rising edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b. sed_s0_h 39 7:0 sed compare pattern sample0[15:8] compare pattern sample0[15:0] is the word that is compared with data sample 0 captured at the input interface by the rising edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b. sed_s1_l 3a 7:0 sed compare pattern sample1[7:0] compare pattern sample1[15:0] is the word that is compared with data sample 1 captured at the input interface by the falling edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b. sed_s1_h 3b 7:0 sed compare pattern sample1[15:8] compare pattern sample1[15:0] is the word that is compared with data sample 1 captured at the input interface by the falling edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b. sed_s2_l 3c 7:0 sed compare pattern sample2[7:0] compare pattern sample2[15:0] is the word that is compared with data sample 2 captured at the input interface by the rising edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b. sed_s2_h 3d 7:0 sed compare pattern sample2[15:8] compare pattern sample2[15:0] is the word that is compared with data sample 2 captured at the input interface by the rising edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b. sed_s3_l 3e 7:0 sed compare pattern sample3 [7:0] compare pattern sample3[15:0] is the word that is compared with data sample 3 captured at the input interface by the falling edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b. sed_s3_h 3f 7:0 sed compare pattern sample3[15:8] compare pattern sample3[15:0] is the word that is compared with data sample 3 captured at the input interface by the falling edge of dci. set dac spi select = 0 to configure port a. set dac spi select = 1 to configure port b.
ad9148 rev. 0 | page 37 of 76 register name addr (hex) bit name function default sed control/status 40 7 sed compare enable enables the sed circuitry. 0 6 port b error detected status of last compare on port b. 0 5 port a error detected status of last compare on port a. 0 3 auto-clear enable enables the auto reset after eight valid sample sets. 0 2 port b compare failed fail status determined for last sample set on port b. 0 1 port a compare failed fail status determined for last sample set on port a. 0 0 compare passed pass status determined for last sample set. 0 sed_r_l 41 7:0 sed status rising edge samples[7:0] sed status rising edge samples[15:0] indicate which bits were received in error. read- only set dac spi select = 0 to read back errors on port a. set dac spi select = 1 to read back errors on port b. sed_r_h 42 7:0 sed status rising edge samples[15:8] sed status rising edge samples[15:0] indicate which bits were received in error. read- only set dac spi select = 0 to read back errors on port a. set dac spi select = 1 to read back errors on port b. sed_f_l 43 7:0 sed status falling edge samples[7:0] sed status falling edge samples[15:0] indicate which bits were received in error. read- only set dac spi select = 0 to read back errors on port a. set dac spi select = 1 to read back errors on port b. sed_f_h 44 7:0 sed status falling edge samples[15:8] sed status falling edge samples[15:0] indicate which bits were received in error. read- only set dac spi select = 0 to read back errors on port a. set dac spi select = 1 to read back errors on port b. i gain control 50 7:0 igain igain[7:0] is a value that directly scales the samples written to the idac. the bit weighting is msb = 2 1 and lsb = 2 ?6 , which yields a multiplier range of 0 to 3.984375. 40 set dac spi select = 0 to configure dac 1 path. set dac spi select = 1 to configure dac 3 path. q gain control 51 7:0 qgain qgain[7:0] is a value that directly scales the samples written to the qdac. the bit weighting is msb = 2 1 and lsb = 2 ?6 , which yields a multiplier range of 0 to 3.984375. 40 set dac spi select = 0 to configure dac 2 path. set dac spi select = 1 to configure dac 4 path.
ad9148 rev. 0 | page 38 of 76 register name addr (hex) bit name function default ftw (lsb) 54 7:0 ftw[7:0] see register 0x57. 0 ftw 55 7:0 ftw[15:8] see register 0x57. 0 ftw 56 7:0 ftw [23:16] see register 0x57. 0 ftw (msb) 57 7:0 ftw [31:24] ftw[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip nco. the frequency is not updated when the ftw registers are written. the values are only updated when register 0x5a[2] transitions from 0 to 1. 0 phase offset msb 58 7:0 nco phase offset[15:8] see register 0x59. 0 phase offset lsb 59 7:0 nco phase offset[7:0] nco phase offset[15:0] sets the phase of the complex carrier signal when the nco is reset. the phase offset spans between 0o and 360o. each bit represents an offset of 0.0055. value is in twos complement format. 0 dds/mod control 5a 7 bypass dds/mod 1 = bypass nco. 1 5 frame nco reset ack 1 = indicates that the nco has been reset due to an extended framex_x pulse signal. 0 4 frame nco reset request 0 1 = the nco is reset on the first extended framex_x pulse after this bit transitions from 0 to 1. 0 3 ftw update ack 1 = indicates that the ftw has been updated with the spi value. 0 2 ftw update request 0 1 = ftw is updated with the spi value on a 0-to-1 transition of this bit. 0 0 sideband select 0 = the modulator output high-side image. 0 1 = the modulator output low-side image. the image is spectrally inverted compared to the input data. die temp control 0 5c 1 latch temp data 0 1 = latches temp sensor data. this should be completed before the die temp[15:0] is readback. 0 0 temp sensor power-down 1 = powers down the aux adc that converts die temperature. 1 die temp control 1 5d 7:0 00001010 set these bits to 00001010 for optimal temperature sensor operation. 100000 die temp (lsbs) 5e 7:0 die temp[7:0] die temp[15:0] indicates the approximate die temperature. read- only die temp (msbs) 5f 7:0 die temp[15:8] die temp[15:0] indicates the approximate die temperature. read- only dci delay 72 1:0 dci delay programmable delay added dci. 00 00 = no added delay. 01 = 200 ps delay. 10 = 400 ps delay. 11 = 600 ps delay. lvds pad ctrl 74 3:0 lvds input resistance programmable lvds input resistance (see table 15 ). 1101
ad9148 rev. 0 | page 39 of 76 input data ports the ad9148 can operate in three data input modes: dual-port mode, single-port mode, and byte mode. in dual-port mode, dac 1 and dac 2 receive data from port a, and dac 3 and dac 4 receive data from port b. in single-port mode, all four dacs receive data from port a. in byte mode, all four dacs receive data from port a, but the port is split into two 8-bit wide buses. in all modes, the data input timing is relative to a dci signal provided with the data. each data sample, by default, is expected to be formatted as an msb sent to bit 15 and an lsb sent to bit 0 for each port. the ad9148 contains an option to swap the bus (register 0x03[4]). when this bus swap bit is set, the msb should be sent to bit 0, and the lsb should be sent to bit 15 for each port. single-port mode in single-port mode, a frame signal must be provided along with the dci signal and the data. the frame signal indicates to which dac the data is intended. when frame goes high, the first data-word goes to dac 1, and the second data-word goes to dac 2. when frame goes low, the first data-word goes to dac 3, and the second data-word goes to dac 4. this pattern repeats continuously as illustrated in figure 47 . dual-port mode in dual-port mode, the dci signal indicates to which dac the data is intended. on the rising edge of dci, data is latched into dac 1 and dac 3. on the falling edge of dci, data is latched into dac 2 and dac 4. this pattern repeats continuously. framea a[15:0] dac1 dac2 dac3 dac4 dac1 dac2 dac3 dac4 dcia 08910-047 there is a spi programmable option (register 0x14[6]) to provide one dci for both input ports or two dcis, where each dci is associated with one input port. two dcis are useful when the data for each port is coming from a different data source. these cases are illustrated in figure 45 and figure 46 . dcia a[15:0] dac1 dac2 dac1 dac2 dac1 dac2 dac1 dac2 dac3 dac4 dac3 dac4 dac3 dac4 dac3 dac4 b[15:0] 08910-045 figure 47. timing diagram for single-port mode each data sample, by default, is expected to be formatted as an msb sent to bit 15 and an lsb sent to bit 0. when the bus swap bit is set (register 0x03[4]), the msb should be sent to bit 0, and the lsb should be sent to bit 15 for each port. figure 45. timing diagram for dual-port mode, one dci the frame signal is sampled with the same internal signal as the data and has the same set-up and hold timing relative to dci. if desired, only the first frame pulse needs to be generated. this initializes the internal clock phases inside the device, and data latches just as if the periodic frame signal were sent. dcia a[15:0] dac1 dac2 dac1 dac2 dac1 dac2 dac1 dac2 dac3 dac4 dac3 dac4 dac3 dac4 dac3 dac4 b[15:0] dcib 08910-046 figure 46. timing diagram for dual-port mode, two dci
ad9148 rev. 0 | page 40 of 76 byte mode in byte mode, a frame signal must be provided along with the dci signal and the data. the most significant byte of the data should correspond with dci being high, and the least significant byte of the data should correspond with dci being low. the frame signal indicates to which dac the data is intended. when frame is high, data on the top half of the port (a[15:8]) is sent to dac 1 and data on the bottom half of the port (a[7:0]) is sent to dac 3. when the frame is low, data on the top half of the port is sent to dac 2 and data on the bottom half of the port is sent to dac 4. this pattern repeats continuously as shown in figure 48 . framea a[15:8] dac1h dac1l dac2h dac2l dac1h dac1l dac2h dac2l a[7:0] dac3h dac3l dac4h dac4l dac3h dac3l dac4h dac4l dcia 08910-048 figure 48. timing diagram for byte mode the ad9148 also includes a byte swap feature. by default, the bytes should be formatted as an msb sent to bit 15 on bus 1 and bit 7 on bus 2. when byte swap is enabled (register 0x03[2]), an msb should be sent to bit 8 on bus 1 and bit 0 on bus 2. this is described in table 14 . table 14. byte swap formatting byte swap byte a[15:8] a[7:0] 0 msb data set 1[15:8] data set 2[15:8] 0 lsb data set 1[7:0] data set 2[7:0] 1 msb data set 1[8:15] data set 2[8:15] 1 lsb data set 1[0:7] data set 2[0:7] data interface options t o enable optimization of the data interface, some additional options have been provided in the following registers: ? data format (register 0x03) ? data receiver control (register 0x14) ? data receiver status (register 0x15) depending on the data rate and dci vs. data skew, the internal dci can be inverted to meet the valid data timing window.
ad9148 rev. 0 | page 41 of 76 frame input levels the frame lvds receiver inputs (framea_x and frameb_x) have a slightly different specification than the lvds standard. the maximum input low voltage (v il ) of the frame receiver is specified at 1.125 v. in the worst case, when the common-mode voltage of the lvds transmitter is at its maximum level of 1.375 v, the required peak-to-peak voltage swing at the frame lvds receiver input should be larger than 2 (1.375 ? 1.125) = 500 mv. to guarantee this voltage swing, it is recommended that the lvds transmitters on the fpga or the asic have a setting with their typical differential output voltage equal to or larger than 500 mv. to help further increase the voltage swing at the frame receiver input, the lvds input resistance of the frame receiver can be adjusted by register 0x74. table 15 shows the input resistance values with various register settings. the default value is 0x0d. the input voltage swing is proportional to the input resistance. the following equation can be used to calculate the peak-to-peak voltage swing at the frame receiver input assuming there is no trace loss on the pcb: v i p-p = v o p-p 90 resistance inpu t lvds where: v i p-p = the peak-to-peak voltage swing at the frame receiver input. v o p-p = the specified peak-to-peak voltage swing at the lvds transmitter output. table 15. lvds input resistance register value (register 0x74) lvds input resistance value () 0x0d 90 0x 0c 96 0x 0b 103 0x 0a 112 0x 09 119 frame receiver input voltage swing example g iven the following: lvds transmitter output common-mode voltage, v o, cm = 1.3 v. lvds transmitter output peak to peak voltage swing, v o p-p = 350 mv. lvds trace resistance, r pcb = 2 . the range of the output voltage swing is 1.125 v to 1.475 v, which meets the maximum input low voltage requirement of the frame receiver with no trace loss. there is roughly 2% loss on the voltage swing in this example due to the finite trace resistance. to account for the loss on the pcb traces, the lvds input resistance can be increased to boost the voltage swing at the input. by writing 0x0c to register 0x74, the lvds input resistance increases by 6 . the input voltage swing can be calculated as v i p-p = 350 mv 90 96 98% = 365 mv
ad9148 rev. 0 | page 42 of 76 fifo operation dac1 and dac2 32 32 bits int dcia dcib dacclk data port a data port b data paths data assembler input latch data assembler input latch reg 0 reg 1 reg 2 reg 3 reg 4 reg 5 reg 6 reg 7 reg 0 reg 1 reg 2 reg 3 reg 4 reg 5 reg 6 reg 7 32 dac3 and dac4 32 32 data paths 32 write ptr reset write ptr reset read ptr reset sync logic fifo rate/ data rate fifo a ofs[2:0] fifo b ofs[2:0] 32 bits frameb frame a logic read pointer a read pointer b 32 32 interface mode one dci write ptr b write ptr a 08910-049 figure 49. block diagram of fifo the ad9148 contains two 32-bit wide, 8-word deep fifos (one per dual dac) designed to relax the timing relationship between the data arriving at the dac input ports and the internal dac data rate clock. the fifos can also be used to provide an adjustable pipeline delay between the dcix clocks and the dacclk allowing realignment of data input in a multichip system. this significantly increases the timing budget of the interface. figure 49 shows the block diagram of the datapath through the fifo. the data is latched into the device, is formatted, and is then written into the fifo register determined by the fifo write pointer. the value of the write pointer is incremented every time a new word is loaded into the fifo. meanwhile, data is read from the fifo register determined by the read pointer and fed into the digital datapath. the value of the read pointer is updated every time data is read into the datapath from the fifo. this happens at the data rate, that is the dacclk rate divided by the interpolation ratio. the difference between the write and read pointers represents the fifo pipeline delay and is important to take into account when understanding the overall pipeline delay of the ad9148. in single-port and byte interface modes, the incoming digital data is sampled at twice the data rate (dcia). the data is then assembled based on the interface mode. at the output of the data assembler block, the data samples for dac 1 and dac 2 are written to fifo a and the data samples for dac 3 and dac 4 are written to fifo b at the data rate. valid data is transmitted through the fifo as long as the fifo does not overflow or become empty. an overflow or empty condition of the fifo is the same as the write pointer and the read pointer being equal. when both pointers are equal, an attempt is made to read and write a single fifo register simultaneously. this simultaneous register access leads to unreliable data transfer through the fifo and must be avoided.
ad9148 rev. 0 | page 43 of 76 nominally, data is written to the fifo at the same rate as data is read from the fifo. this keeps the data level in the fifo constant. if data is written to the fifo faster than data is read, the data level in the fifo increases. if the data is written to the device slower than data is read, the data level in the fifo decreases. for a maximum timing margin, the fifo level should be maintained near half full, which is the same as maintaining a difference of 4 between the write pointer and read pointer values. synchronizing and resetting the fifo to avoid any concurrent reads and writes to the same fifo address and to assure a fixed pipeline delay, it is important to reset the state of the fifo pointers to known states. the pipeline delay in the ad9148 comes from two sources, fifo delay and the delay though the signal processing in the dac. to assure a fixed and predictable pipeline delay in the signal processing, the fifo read operation is synchronized with the dacclk and, more importantly, in case of interpolation, its divided down version so that the same edge of the slowest clock in the signal processing reads the same data in the fifo. the synchronization is performed by resetting the fifo read pointer to a known state relative to the slowest clock used in the signal processing. this synchronization is enabled by setting bit 7 in register 0x10 to 1, and it uses the refclk/sync signal for its reference. to manage the fifo pipeline delay, the fifo write pointer must be synchronized with the read pointer to avoid concurrent access to the fifo and to potentially compensate for any data input phase mismatch. this synchronization can be performed either at the data rate (see the data rate synchronization section) or at the fifo rate (see the fifo rate synchronization section). fifo synchronization modes t o benefit from the advantages of the fifo functionality in the different modes of operations, pll on/off, standalone, or multi- chip synchronization, the fifo can operate in the following ways: ? synchronization at the data rate ? synchronization at the fifo rate (data rate/fifo depth) ? no synchronization as discussed in the input data ports section, in single-port mode and byte mode, the frame input is used as a data select signal that indicates to which dac the input data is intended to be written. when synchronization is needed, the frame signal is given another function, initializing the fifo write pointer address. when the frame signal is asserted high for at least the time interval needed to load complete data to the four dacs (which correspond to one dci period in dual-port mode and two dci periods in single-port mode or byte mode), the fifo write pointer is reset to a value dependent on the synchronization mode selected and the fifo phase offset bits of the corresponding fifo status/control port x register, register 0x17 or register 0x19. data rate synchronization in this mode, the refclk/sync signal is used to reset the fifo read pointer to 0. the edge of the clk used to sample the sync signal is selected by bit 3 of register 0x10. if the pll is used, refclk is used as a sync signal, and the fifo read pointer is reset at the refclk rate divided by 64. the data rate synchronization is selected by setting bit 6 of register 0x10 to 0. as previously mentioned, the frame signal is used to reset the fifo write pointer. when the frame is asserted, the fifo write pointer is reset to the address defined in bits[2:0] of the corresponding fifo status/control port x register (register 0x17 or register 0x19) the next time the read pointer becomes 0 (see figure 50 ). the data rate synchronization, the write pointer of the fifo, and the read pointer of the fifo are synchronized at the sync rate and have a fixed phase offset. 34567 01234 56 701234567012 345670123456 012344567012 fifo_a write reset fifo_b write reset sync rdptra rdptrb framea wrptra wrptrb reset value for register 0x17[2:0] = 0b100 frameb reset value for register 0x19[2:0] = 0b100 08910-050 figure 50. timing of the frame input vs. write pointer value in data rate synchronization fifo rate synchronization in this mode, the refclk/sync signal is used to reset the fifo read pointer to 0. the edge of the clk_x used to sample the sync signal is selected by bit 3 of register 0x10. as previously mentioned, the frame signal is used to reset the fifo write pointer. in the fifo rate synchronization mode, the fifo write pointer is reset immediately after the frame signal is asserted high for at least the time interval needed to load complete data to the four dacs, and the fifo write pointer is reset to the address defined in bits[2:0] of the corresponding fifo status/control port x register, register 0x17 or register 0x19 (see figure 51 ) . 01234 56701 23 6 44567012345 012345670123 2346 0 12 3456 7 fifo_a write reset fifo_b write reset reset value for register 0x17[2:0] = 0b100 reset value for register 0x19[2:0] = 0b110 fifo_a and fifo_b read reset sync rdptra rdptrb framea w rptra w rptrb frameb 08910-051 figure 51. timing of the frame input vs. write pointer value in fifo rate synchronization
ad9148 rev. 0 | page 44 of 76 no synchronization in this mode, bit 7 in register 0x10 is set to 0, the pipeline delay in the signal processing is not controlled, and the read pointer of the fifo is never reset. however, to assure that the fifo can operate safely and there is no concurrent access to fifo from the write and read pointer to the same address, it is important to ensure that the phase offset between the two pointers is greater than 2. in consequence, the only fifo reset that can be used safely is the data rate synchronization, bit 6 of register 0x10 set to 0, where the fifo is reset with a fixed offset of 4 between the write and read pointers. because there is no sync signal, the reset of the fifo write pointer can only be done by a frame signal or an spi command. fifo reset commands depending on the configuration of the system, the fifo reset can be done manually or periodically for a multichip system. the ad9148 provides two ways to resetting the fifo pointers: spi interface or periodic reset using the frame signal. the spi also gives access to each fifo phase offset in bits [2:0] of the corresponding fifo status/control registers, register 0x17 and register 0x19. the value in these three bits corresponds either to the offset between the write and read pointer in the data rate synchronization or to the absolute address of the fifo write pointer in the fifo rate synchronization. spi command for manual reset if a manual reset is acceptable, the fifo pointer addresses can be reset using the spi interface. to initialize the fifo data level through the spi, bit 3 of register 0x17 (fifo port a) or bit 3 of register 0x19 (fifo port b) should be toggled from 0 to 1 and back. when the write to the register is complete, the corresponding fifo data level is initialized. th e recommended procedure for a spi fifo data level initialization is 1. request fifo port a or fifo port b level reset by setting bit 3 in register 0x17 or bit 3 in register 0x19 to logic 1. the fifo phase offset, bits [2:0] in register 0x17 or bits [2:0] in register 0x19, should also be written at the same time to set the desired value of offset between the fifo write and read pointers. 2. verify that the part acknowledges the request by ensuring that bit 4 in register 0x17 or bit 4 in register 0x19 is set to logic 1. 3. remove the request by resetting bit 3, register 0x17 or bit 3, register 0x19 to 0. 4. the fifo spi aligned flag in the event flag 0 register, bit 2 in register 0x06, is set when the reset of the write pointer has been realized. bit 4 in register 0x17 or bit 4 in register 0x19 is reset to 0 to indicate which fifo has generated this flag. note that the spi writes to register 0x17 or register 0x19 should be done while maintaining a constant value in the fifo phase offset bits. fifo reset using frame signal the fifo pointers can also be reset using the frame signals. if only one dci is used, only the framea signal is used for the fifo reset. this mode is enabled by setting bit 6 in register 0x10. a s discussed in the fifo synchronization modes section, the frame input is used to initialize the fifo data level value. when the frame signal is asserted high for at least the time interval needed to load the complete data to the four dacs, the write pointer is reset depending on the mode of synchronization chosen. ? data rate synchronization (default), bit 6 of register 0x10, is set to 0. when read pointer reaches 0, write pointer reset to fifo offset phase. ? fifo rate synchronization, bit 6 of register 0x10, is set to 1. on the rising edge of the frame signal, write pointer reset to fifo start level. monitoring the fifo status the fifo initialization and status can be read from register 0x17. this register provides information about the fifo initialization method and whether the initialization was successful. the msb of register 0x17 is a fifo warning flag that can optionally trigger a device irq . this flag is an indication that the fifo is close to emptying (fifo level is 1) or overflowing (fifo level is 7). this is an indication that the data may soon be corrupted, and action should be taken. the fifo data level can be read from register 0x18 at any time. the spi reported fifo data level is denoted as a 7-bit thermometer code of the write counter state relative to the absolute read counter being 0. the optimum fifo data level of four is, therefore, reported as a value of 00001111 in the status register. note that, depending on the timing relationship between dci and the main dacclk, the fifo level value can be off by a 1 count. therefore, it is important to keep the difference between the read and write points to at least 2.
ad9148 rev. 0 | page 45 of 76 device synchronization synchronizing multiple devices system demands may require that the outputs of multiple dacs be synchronized with each other or with a system clock. systems that support transmit diversity or beam-forming, where multiple antennas are used to transmit a correlated signal, require multiple dac outputs to be phase aligned with each other. systems with a time-division multiplexing transmit chain may require one or more dacs to be synchronized with a system-level reference clock. multiple devices are considered synchronized to each other when the state of the clock generation state machines is identical for all parts and time aligned data is being read from the fifos of all parts simultaneously. devices are considered synchronized to a system clock when there is a fixed and known relationship between the clock generation state machine and the data being read from the fifo and a particular clock edge of the system clock. the ad9148 has provisions for enabling multiple devices to be synchronized to each other or to a system clock. the ad9148 supports synchronization in two different modes, data rate mode and fifo rate mode. the two modes are distinguished by the lowest rate clock that the synchronization logic attempts to synchronize. in data rate mode, the input data rate represents the lowest synchronized clock. in fifo rate mode, the fifo rate, which is the data rate divided by the fifo depth of 8, represents the lowest rate clock. the advantage of the fifo rate synchronization is increased setup and hold times of dci relative to the clk input. when in data rate synchronization mode, the elasticity of the fifo is not used to absorb timing variations between the data source and dac, resulting in tighter setup and hold time requirements. the method chosen for providing the dac sampling clock directly impacts the synchronization methods available. when the device clock multiplier is used, only data rate synchronization is available. when the dac sampling clock is sourced directly, both data rate mode and fifo rate mode synchronization are available. synchronization with clock multiplication when using the clock multiplier to generate the dacclk, the refclk/sync input signal acts as both the reference clock for the pll-based clock multiplier and as the synchronization signal. to synchronize devices, the refclk/sync signal must be distributed with low skew to all of the devices to be synchronized. skew between the refclk/sync signals of different devices show up directly as a timing mismatch at the dac outputs. the frequency of the refclk/sync signal is typically equal to the input data rate. the frame signal and dci signals can be created in the fpga along with the data. a circuit diagram of a typical configuration is shown in figure 52 . s ystem cloc k fpga low skew clock driver matched length traces matched length traces refclk/sync frame dci refclk/sync frame dci out1 out2 08910-052 figure 52. typical circuit diagram for synchronizing devices with clock multiplication enabled
ad9148 rev. 0 | page 46 of 76 the following procedure outlines the steps required to synchronize multiple devices. the procedure assumes that the refclk/sync signal is applied to all of the devices and the pll of each device is phase locked to it. each individual device must follow this procedure. th e procedure for synchronization when using the pll follows: 1. configure for data rate, periodic synchronization by writing 0xc0 to the sync control register (register 0x10). 2. read the sync status register (register 0x12) and verify that the sync locked bit (bit 6) is set high indicating that the device achieved back-end synchronization and that the sync lost bit (bit 7) is low. these levels indicate that the clocks are running with a constant and known phase relative to the sync signal. 3. reset the fifo by strobing the frame signal high for at least the time interval needed to load complete data to the four dacs. resetting the fifo ensures that the correct data is being read from the fifo. this completes the synchronization procedure, and at this stage, all devices should be synchronized. to maintain synchronization, the skew between refclk/sync signals of the devices must be less than t skew nanoseconds. there is also a setup and hold time to be observed between the dci and data of each device and the refclk/sync signal. when resetting the fifo, the frame signal must be held high for at least the time interval needed to load complete data to the four dacs (one dci period for dual-port mode and two dci periods for single-port or byte mode). a timing diagram of the input signals is shown in figure 53 . the example in figure 53 shows a refclk/sync frequency equal to the data rate. whereas this is the most common situation, it is not strictly required for proper synchronization. any refclk/sync frequency that satisfies the following equations is acceptable: f sync = f dacclk /2 n and f sync f data where n = 1, 2, 3, or 4. for example, a configuration with 4 interpolation and clock frequencies of f vco = 1600 mhz, f dacclk = 800 mhz, and f data = 200 mhz, f sync = 100 mhz would be a viable solution. refclk(1) refclk(2) dci(2) frame(2) t skew t su_dci t h_dci 08910-053 figure 53. timing diagram required for synchronizing two devices
ad9148 rev. 0 | page 47 of 76 sample rate clock fpga low skew clock driver low skew clock driver matched length traces clk frame dci out1 out2 sync clock refclk/sync clk frame dci refclk/sync matched length traces 08910-054 figure 54. typical circuit diagram for synchronizing devices to a system clock synchronization with direct clocking when directly sourcing the dac sample rate clock to clk, a separate refclk/sync input signal is required for synchronization. to synchronize devices, the clk signals and the refclk/sync signals must be distributed with low skew to all of the devices being synchronized. this configuration is shown below in figure 54 . data rate mode synchronization the following procedure outlines the steps required to synchronize multiple devices in data rate mode. the procedure assumes that the clk and refclk/sync signals are applied to all of the devices. each individual device must follow the procedure. the procedure for data rate synchronization when directly sourcing the dac sampling clock follows: 1. configure for data rate, periodic synchronization by writing 0xc0 to the sync control register (register 0x10). additional synchronization options are available (see the additional synchronization features section). 2. poll the sync locked bit (bit 6, register 0x12) to verify that the device is back-end synchronized. a high level on this bit indicates that the clocks are running with a constant and known phase relative to the sync signal. 3. reset the fifo by strobing the frame signal for at least the time interval needed to load complete data to the four dacs resetting the fifo ensures that the correct data is being read from the fifo of each of the devices simultaneously. this completes the synchronization procedure, and at this stage, all devices should be synchronized. to ensure that each of the dacs are updated with the correct data on the same dacclk edge, two timing relationships must be met on each dac. dci (and data) must meet the setup and hold times with respect to the rising edge of clk, and refclk/sync must also meet the setup and hold time with respect to the rising edge of clk. when resetting the fifo, the frame signal must be held high for at least the time interval needed to load complete data to the four dacs (one dci period for dual- port mode and two dci periods for single-port or byte mode). when these conditions are met, the outputs of the dacs will be updated within t skew + t outdly nanoseconds of each other. a timing diagram that illustrates the timing requirements of the input signals is shown in figure 55 . clk(1) clk(2) sync(2) frame(2) dci(2) t skew t h_dci t su_dci t h_sync t su_sync 08910-055 figure 55. synchronization signal timing requirements in data rate mode, 2 interpolation figure 55 shows the synchronization signal timing with 2 interpolation, so that f dci = ? f clk . the refclk/sync input is shown equal to the dci rate. the maximum frequency at which the device can be resynchronized in data rate mode can be expressed as n data sync f f 2 = for any positive integer, n.
ad9148 rev. 0 | page 48 of 76 generally, for values of n equal to or greater than 3, the fifo rate synchronization mode is chosen. fifo rate mode synchronization the following procedure outlines the steps required to synchronize multiple devices in fifo rate mode. the procedure assumes that the clk and refclk/sync signals are applied to all of the devices. each individual device must follow the procedure. the procedure for fifo rate synchronization when directly sourcing the dac sampling clock follows: 1. configure for fifo rate, periodic synchronization by writing 0x80 to the sync control register (register 0x10). additional synchronization options are available and are described in the additional synchronization features section. 2. poll the sync locked bit (bit 6, register 0x12) to verify that the device is back-end synchronized. a high level on this bit indicates that the clocks are running with a constant and known phase relative to the sync signal. 3. reset the fifo by strobing the frame signal high for at least the time interval needed to load complete data to the four dacs. resetting the fifo ensures that the correct data is being read from the fifo of each of the devices simultaneously. this completes the synchronization procedure, and at this stage, all devices should be synchronized. to ensure that each of the dacs is updated with the correct data on the same dacclk edge, two timing relationships must be met on each dac. dci (and data) must meet the setup and hold times with respect to the rising edge of clk, and refclk/ sync must also meet the setup and hold time with respect to the rising edge of clk. when resetting the fifo, the frame signal must be held high for at least the time interval needed to load complete data to the four dacs (one dci period for dual- port mode, and two dci periods for single-port or byte mode). when these conditions are met, the outputs of the dacs will be updated within t skew + t outdly nanoseconds of each other. a timing diagram that illustrates the timing requirements of the input signals is shown in figure 56 . clk(1) clk(2) sync(2) frame(2) dci(2) t skew t h_sync t su_sync 08910-056 figure 56. synchronization signal timi ng requirements in fifo rate mode, 2 interpolation figure 56 shows the synchronization signal timing with 2 interpolation, so that f dci = ? f clk . the refclk/sync input is shown equal to the fifo rate. the maximum frequency at which the device can be resynchronized in fifo rate mode can be expressed as n data sync f f 28 = for any positive integer, n. additional synchroniation features the synchronization logic incorporates additional features that provide means for querying the status of the synchronization and for improving the robustness of the synchronization. for more information on these features, see the sync status bits section and the timing optimization section. sync status bits when the sync locked bit (bit 6, register 0x12) is set, it indicates that the synchronization logic has reached alignment. this is determined when the clock generation state machine phase is constant. this takes between (11 + averaging) 64 and (11 + averaging) 128 dacclk cycles. this bit may optionally trigger an irq , as described in the section. interrupt request operation when the sync lost bit (bit 7, register 0x12) is set, it indicates that a previously synchronized device has lost alignment. this bit is latched and remains set until cleared by overwriting the register. this bit may optionally trigger an irq as described in the section. interrupt request operation timing optimization the refclk/sync signal is sampled by a version of the dacclk. if sampling errors are detected, the opposite sampling edge can be selected to improve the sampling point. the sampling edge can be selected by setting bit 3, register 0x10 (1 = rising and 0 = falling). the synchronization logic resynchronizes when a phase change between the refclk/sync signal and the state of the clock generation state machine exceeds a threshold. to mitigate the effects of jitter and prevent erroneous resynchronizations, the relative phase can be averaged. the amount of averaging is set by the sync averaging bits (bits[2:0], register 0x10) and can be set from 1 to 128. the higher the number of averages, the more slowly the device recognizes and resynchronizes to a legitimate phase correction. generally, the averaging should be made as large as possible while still meeting the allotted resynchronization time interval.
ad9148 rev. 0 | page 49 of 76 interface timing the timing diagram for the digital interface port is shown in figure 58 . the sampling point of the data bus nominally occurs 250 ps after each edge of the dci signal and has an uncertainty of 250 ps when the dci delay is set to 00b (register 0x72[1:0]), as illustrated by the sampling interval. the data and frame signals must be valid throughout this sampling interval. the data and frame signals may change at any time between sampling intervals. the setup (t s ) and hold (t h ) times with respect to the edges are shown in figure 58 . the minimum setup and hold times are shown in table 16 . table 16. data port setup and hold times dci delay (register 0x72, bits[1:0]) minimum setup time, t s (ns) minimum hold time, t h (ns) 00 ?0.02 0.52 01 ?0.16 0.78 10 ?0.28 1.03 11 ?0.36 1.16 the data interface timing can be verified by using the sed circuitry. see the interface timing validation section for details. in data rate mode with synchronization enabled, a second timing constraint between dci and dacclk must be met in addition to the dci-to-data timing shown in table 17 . in data rate mode, only one fifo slot is being used. the dci to dacclk timing restriction is required to prevent data being written to and read from the fifo slot at the same time. the required timing between dci and dacclk is shown in figure 57 . dci dacclk/ refclk t data t sdci t hdci sampling interval 08910-057 figure 57. timing diagram for input data port (data rate mode with sync on) table 17. dci to dacclk setup and hold times vs. dci delay value dci delay (register 0x72,bits[1:0]) minimum setup time, t sdci (ns) minimum hold time, t hdci (ns) 00 ?0.06 0.85 01 ?0.22 1.14 10 ?0.36 1.43 11 ?0.45 1.59 t data t s t h sampling interval dci dat a sampling interval 08910-058 figure 58. timing diagram for input data ports
ad9148 rev. 0 | page 50 of 76 digital data path the block diagram in figure 59 shows the functionality of the complex digital data path. the digital processing includes a premodulation block, a programmable complex filter, three half-band interpolation filters with built-in coarse modulation, a quadrature modulator with a fine resolution nco as well as phase, gain, and offset adjustment blocks. hb2 premod f s /2 hb1 hb3 digital phase/gain/ offset adj prog sinc ?1 filter 08910-059 figure 59. block diagram of digital data path there are two complex digital data paths that feed the four dacs. each digital data path accepts i and q data streams and processes them as a quadrature data stream, resulting in two quadrature data streams. all of the signal processing blocks can be used when the input data stream is represented as complex data. the data path can be used to process an input data stream representing four independent real data streams as well; however, the functionality is somewhat restricted. the premodulation block can be used, as well as any of the nonshifted interpolation filter modes. premodulation the half-band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of ? of their input data rate. the premodulation block provides a digital upconversion of the incoming waveform by ? of the incoming data rate, f data. functionally, the premodulation multiplies the incoming data samples alternatively by +1 and ?1. this can be used to frequency shift baseband input data to the center of the interpolation filters pass band. programmable inverse sinc filter the ad9148 provides a programmable inverse sinc filter to compensate the dac roll-off over frequency. because this filter is implemented before the interpolation filter, its coefficients must be changed depending on the interpolation rate and dac output center frequency. filter structure the programmable inverse sinc filter is a nine-tap complex fir filter using complex conjugate coefficients. the z-transfer function is () 8 0 7 1 6 2 5 3 4 4 3 3 2 2 1 10 ? ? ? ? ? ? ? ? ++++ ++++= += + + = where: x i and x q are the in-phase (real) and quadrature (imaginary) filter input, respectively. y i and y q are the in-phase (real) and quadrature (imaginary) filter output, respectively. h i and h q are the in-phase (real) and quadrature (imaginary) filter coefficients, respectively. c 0 , c 1 , c 2 , c 3 , and c 4 are the complex filter coefficient, and c x their complex conjugate. the filter coefficients must be calculated and programmed into the ad9148 registers to perform the operation desired. filter implementation to perform the complex filtering of the complex input, the filter is divided in four filters working in parallel, two sets of h i and two sets of h q (see figure 60 ). ( ) ( ) () +?+?= +?+=+ x i h i h q y i y q x q h i h q + ? + + 08910-060 figure 60. complex filter implementation the coefficients for the filter are stored in spi register 0x20 to register 0x27 in twos-complement format. they have variable length, three bits to 10 bits.
ad9148 rev. 0 | page 51 of 76 table 18. programmable inverse sinc fi lter coefficient widths and ranges coefficient width minimum maximum c 0 in-phase (real) 3 100b 011b ?4 3 c 0 quadrature (imaginary) 3 0100b 011b ?4 3 c 1 in-phase (real) 4 1000b 0111b ?8 7 c 1 quadrature (imaginary) 4 1000b 0111b ?8 7 c 2 in-phase (real) 5 10000b 01111b ?16 15 c 2 quadrature (imaginary) 5 10000b 01111b ?16 15 c 3 in-phase (real) 7 1000000b 0111111b ?64 63 c 3 quadrature (imaginary) 7 1000000b 0111111b ?64 63 c 4 in-phase (real) 10 1000000000b 0111111111b ?1024 1023 c 4 quadrature (imaginary) 10 1000000000b 0111111111b ?1024 1023 the real and imaginary filters are implemented using the structure described in figure 61 and figure 62 . input n output n z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 + c 0real c 1real c 2real c 3real c 4real c 5real + + + + + + + + + + + + + + + + + + + 08910-061 figure 61. real filt er implementation input n output n z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 z ?1 + ? c 0img c 1img c 2img c 3img c 4img c 5img + ? + + + ? + + + ? + + + ? + + + + 08910-062 figure 62. imaginary fi lter implementation the ad9148 evaluation tools provide software that allows for the processing of the filter coefficients based on the dac sampling frequency, the amount of interpolation used (combination of hb1, hb2, and hb3), and the desired center frequency. this center frequency is limited to [?( f dac /2, f dac /2/ int ); f dac /2, f dac /2/ int ] where int is the interpolation rate. when there is no interpolation used, the real filter coefficients can be fixed at (no imaginary coefficients) c 0 = 2 ; c 8 = 2 c 1 = ?4 ; c 7 = ?4 c 2 = 10 ; c 6 = 10 c 3 = ?35 ; c 5 = ?35 c 4 = 401 interpolation filters the transmit path contains three interpolation filters. each of the three interpolation filters provides a 2 increase in output data rate. the filters can be casc aded to provide 2, 4, or 8 interpolation ratios. each of the half-band filter stages offers a different combination of bandwidths and operating modes. th e bandwidth of the three half-band filters with respect to the data rate at the filter input is as follows: b andwidth of hb1 = 0.8 f in1 b andwidth of hb2 = 0.5 f in2 bandwidth of hb3 = 0.4 f in3 the usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than 0.001 db and an image rejection of greater than +85 db. as is discussed in the half-band filter 1 (hb1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. the half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. the hb1 filter has four modes of operation, and the hb2 and hb3 filters each have eight modes of operation.
ad9148 rev. 0 | page 52 of 76 2 . 0 half-band filter 1 (hb1) hb1 has four modes of operation, as shown in figure 63 . the shape of the filter response is identical in each of the four modes. the four modes are distinguished by two factors: the filter center frequency and whether the filter modulates the input signal. 0 ?20 ?40 ?60 ?80 ?100 0 1.81.61.41.21.00.80.60.40.2 magnitude (db) ( f in1 ) mode 0 mode 1 mode 3 mode 2 08910-063 figure 63. hb1 filter modes as is shown in figure 63 , the center frequency in each mode is offset by ? of the input data rate (f in1 ) of the filter. mode 0 and mode 1 do not modulate the input signal. mode 2 and mode 3 modulate the input signal by f in1 . when operating in mode 0 and mode 2, the i and q paths operate independently and no mixing of the data between channels occurs. when operating in mode 1 and mode 3, mixing of the data between the i and q paths occurs; therefore, the data input into the filter is assumed complex. table 19 summarizes the hb1 modes. table 19. 2 interpolation filter modes (register 0x1c to register 0x1e) interpolation factor filter modes f center (f dac ) pre-mod hb1 hb2 hb3 2 0 0 off off 0 2 1 1 off off f dac /4 2 0 2 off off f dac /2 2 1 3 off off ?f dac /4 figure 64 shows the pass-band filter response for hb1. in most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. table 20 shows the pass-band flatness and stop-band rejection the hb1 filter supports at different bandwidths. 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 00 0.360.320.280.24 0.20 0.160.120.080.04 magnitude (db) ( f in1 ) . 4 0 08910-064 figure 64. pass-band detail of hb1 table 20. hb1 pass-band and stop-band performance by bandwidth bandwidth (% of f in1 ) pass-band flatness (db) stop-band rejection (db) 80 0.001 85 80.4 0.0012 80 81.2 0.0033 70 82.0 0.0076 60 83.6 0.0271 50 85.6 0.1096 40 half-band filter 2 (hb2) hb2 has eight modes of operation, as shown in figure 65 and figure 66 . the shape of the filter response is identical in each of the eight modes. the eight modes are distinguished by two factors, the filter center frequency and whether the input signal is modulated by the filter. 0 ?20 ?40 ?60 ?80 ?100 02 . 0 1.81.61.41.21.00.80.60.40.2 magnitude (db) ( f in2 ) mode 0 mode 2 mode 4 mode 6 08910-065 figure 65. hb2, even filter modes
ad9148 rev. 0 | page 53 of 76 0 ?20 ?40 ?60 ?80 ?100 02 1.81.61.41.21.00.80.60.40.2 magnitude (db) ( f in2 ) . 0 mode 1 mode 3 mode 7 mode 5 08910-066 figure 66. hb2, odd filter modes as shown in figure 65 and figure 66 , the center frequency in each mode is offset by ? of the input data rate (f in2 ) of the filter. mode 0 through mode 3 do not modulate the input signal. mode 4 through mode 7 modulate the input signal by f in2 . when operating in mode 0 and mode 4, the i and q paths operate independently, and no mixing of the data between channels occurs. when operating in the other six modes, mixing of the data between the i and q paths occurs; therefore, the data input to the filter is assumed complex. tabl e 21 summarizes the hb2 modes. table 21. 4 interpolation filter modes (register 0x1c to register 0x1e) interpolation factor filter modes f center (f dac ) pre-mod hb1 hb2 hb3 4 0 0 0 off 0 4 1 1 1 off f dac /8 4 0 2 2 off f dac /4 4 1 3 3 off 3f dac /8 4 0 0 4 off f dac /2 4 1 1 5 off ?3f dac /8 4 0 2 6 off ?f dac /4 4 1 3 7 off ?f dac /8 figure 67 shows the pass-band filter response for hb2. in most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. table 22 shows the pass-band flatness and stop-band rejection the hb2 filter supports at different bandwidths. 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 00 0.28 0.24 0.20 0.16 0.12 0.08 0.04 magnitude (db) ( f in2 ) . 3 2 08910-067 figure 67. pass-band detail of hb2 table 22. hb2 pass-band and stop-band performance by bandwidth bandwidth (% of f in2 ) pass-band flatness (db) stop-band rejection (db) 50 0.001 85 50.8 0.0012 80 52.8 0.0028 70 56.0 0.0089 60 60 0.0287 50 64.8 0.1877 40 half-band filter 3 (hb3) hb3 has eight modes of operation that function the same as hb2. the primary difference between hb2 and hb3 are the filter bandwidths. table 23 summarizes the filter modes for hb3. table 23. 8 interpolation filter modes (register 0x1c to register 0x1e) interpolation factor filter modes f center (f dac ) pre-mod hb1 hb2 hb3 8 0 0 0 0 0 8 0 2 2 1 f dac /8 8 0 0 4 2 f dac /4 8 0 2 6 3 3f dac /8 8 0 0 0 4 f dac /2 8 0 2 2 5 ?3f dac /8 8 0 0 4 6 ?f dac /4 8 0 2 6 7 ?f dac /8
ad9148 rev. 0 | page 54 of 76 0 . 2 8 figure 68 shows the pass-band filter response for hb3. in most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. table 24 shows the pass-band flatness and stop-band rejection the hb3 filter supports at different bandwidths. 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 0 0.24 0.20 0.16 0.12 0.08 0.04 magnitude (db) ( f in3 ) 08910-068 figure 68. pass-band detail of hb3 table 24. hb3 pass-band and stop-band performance by bandwidth bandwidth (% of f in3 ) pass-band flatness (db) stop-band rejection (db) 40 0.001 85 40.8 0.0014 80 42.4 0.002 70 45.6 0.0093 60 49.8 0.03 50 55.6 0.1 40 the maximum bandwidth can be achieved if the signal carrier frequency is placed directly at the center of one of the filter pass bands. in this case, the entire quadrature bandwidth of the interpolation filter (0.8 f data ) is available. the available signal bandwidth decreases as the carrier frequency of the signal moves away from the center frequency of the filter. the worst-case carrier frequency is one that falls directly between the center frequency of two adjacent filters. figure 69 shows how the signal bandwidth changes as a function of placement in the spectrum and interpolation rate. 0.4 0.3 0.2 0.1 complex bw ( f dac ) dc ?1/2 1/2 ?3/8 3/8 ?1/4 1/4 ?1/8 1/8 f c ( f dac ) 2 mode 4 mode 8 mode carrier frequency 0.075 0.0375 0.15 0 08910-069 figure 69. complex signal bandwidth as a function of output frequency fine modulation the fine modulation makes use of a numerically controlled oscillator, a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. a block diagram of the fine modulator is shown in figure 70 . the fine modulator allows the signal to be placed anywhere in the output spectrum with very fine frequency resolution. interpolation interpolation nco 1 0 ?1 cosine sine i data q data ftw[31:0] spectral inversion out_i out_q + ? nco phase offset word [15:0] 08910-070 figure 70. fine modulator block diagram the quadrature modulator is used to mix the carrier signal generated by the nco with the i and q signal. the nco produces a quadrature carrier signal to translate the input signal to a new center frequency. a complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90 from each other. the frequency of the complex carrier signal is set via the ftw[31:0] value in register 0x54 through register 0x57. the nco operating frequency, f nco , is at the dac rate. the frequency of the complex carrier signal can be set from dc up to f dac /2. the frequency tuning word (ftw) is calculated as 32 2 = dac center f f ftw the generated quadrature carrier signal is mixed with the i and q data. the quadrature products are then summed into the i and q data paths, as shown in figure 70 .
ad9148 rev. 0 | page 55 of 76 when using the fine modulator, the maximum signal bandwidth of 0.8 f data is always achieved. based on these two endpoints, the combined resolution of the phase compensation register is approximately 3.5/1024 or 0.00342 per code. when both i phase adj, bits[9:0] (register 0x28 and register 0x29), and q phase adj, bits[9:0] (register 2a and register 2b), are used, the full phase adjustment range is 3.5. updating the frequency tuning word the frequency tuning word registers are not updated immediately upon writing as the other configuration registers do. after loading the ftw registers with the desired values, bit 2 of register 0x5a must transition from 0 to 1 for the new ftw to take effect. dc offset correction the dc value of the i data path and the q data path can be independently controlled by adjusting i dc offset, bits[15:0], and q dc offset, bits[15:0], values in register 0x2c through register 0x2f. these values are added directly to the data path values. care should be taken not to overrange the transmitted values. phase offset adjustment a 16-bit phase offset may be added to the output of the phase accumulator via the serial port. this static phase adjustment results in an output signal that is offset by a constant angle relative to the nominal signal. this allows the user to phase align the nco output with some external signal, if necessary. this can be especially useful when ncos of multiple ad9148s are programmed for synchronization. the phase offset allows for the adjustment of the output timing between the devices. the static phase adjustment is sourced from the nco phase offset[15:0] value located in re gister 0x58 and register 0x59. figure 71 shows how the dac offset current varies as a function of i dc offset, bits[15:0], and q dc offset, bits[15:0], values. with the digital inputs fixed at midscale (0x000, twos complement data format), figure 71 shows the nominal i outxp and i outxn currents as the dc offset value is swept from 0 to 65,535. because i outxp and i outxn are complementary current outputs, the sum of i outxp and i outxn is always 20 ma. quadrature phase correction 0x0000 0x4000 0x8000 0xc000 0xffff 5 10 15 20 5 10 15 20 0 0 dac offset value i outxn (ma) i outxp (ma) 08910-131 the purpose of the quadrature phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator following the dac. if the quadrature modulator has a phase imbalance, the unwanted sideband appears with significant energy. tuning the quadrature phase adjust value can optimize image rejection in single sideband radios. ordinarily, the i and q channels have an angle of precisely 90 between them. the quadrature phase adjustment is used to change the angle between the i and q channels. when i phase adj, bits[9:0] (register 0x28 and register 0x29), are set to 1000000000b, the i dac output moves approximately 1.75 away from the q dac output, creating an angle of 91.75 between the channels. when i phase adj, bits[9:0] (register 0x28 and register 0x29), are set to 0111111111b, the i dac output moves approximately 1.75 toward the q dac output, creating an angle of 88.25 between the channels. figure 71. dac output currents vs. dc offset value digital gain control the last block in each datapath is an 8-bit scalar (register 0x50 and register 0x51) that can be used for digital gain control. the igain control, bits[7:0] (register 0x50), and qgain control, bits[7:0] (register 0x51), values directly scale the samples written to the idac and qdac, respectively. the bit weighting is msb = 2 1 and lsb = 2 -6 , which yields a multipler range of 0 to 3.984375. the scale factor for each data path is calculated as q phase adj, bits[9:0] (register 2a and register 2b), work in a similar fashion. when q phase adj, bits[9:0] (register 2a and register 2b), are set to 1000000000b, the q dac output moves approximately 1.75 away from the i dac output, creating an angle of 91.75 between the channels. when q phase adj[9:0] is set to 0111111111b, the q dac output moves approximately 1.75 toward the i dac output, creating an angle of 88.25 between the channels. 64 ]0:7[ 64 ]0:7[ qgain or igain rscalefacto take care not to overrange the dac when using a scale factor greater than 1.
ad9148 rev. 0 | page 56 of 76 clock generation dac input clock configurations the ad9148 dac sample clock (dacclk) can be sourced directly or by clock multiplying. clock multiplying employs the on-chip, phased-locked loop (pll) that accepts a reference clock (refclk_x) operating at a submultiple of the desired dacclk rate, most commonly the data input frequency. the pll then multiplies the reference clock up to the desired dacclk frequency, which can then be used to generate all the internal clocks required by the dac. the clock multiplier provides a high quality clock that meets the performance requirements of most applications. using the on-chip clock multiplier removes the burden of generating and distributing the high speed dacclk. the second mode bypasses the clock multiplier circuitry and allows dacclk to be sourced directly through the clk_x pins. this mode enables the user to source a very high quality clock directly to the dac core. sourcing the dacclk directly through the clk_x pins may be necessary in demanding applications that require the lowest possible dac output noise, particularly at higher output frequencies. driving the clk_x and refclk_x inputs the refclk_x and clk_x differential inputs share similar clock receiver input circuitry. figure 1 shows a simplified circuit diagram of the input, along with a recommended drive circuit. the on-chip clock receiver has a differential input impedance of about 10 k. it is self-biased to a common-mode voltage of about 1.25 v. the recommended circuit for driving the input is a pair of ac coupling capacitors and a differential 100 termination. the minimum input drive level to either of the clock inputs is 100 mv ppd. the optimal performance is achieved when the clock input signal is between 500 mv ppd and 1.6 v ppd. whether using the on-chip clock multiplier or sourcing the dacclk directly, it is necessary that the input clock signal to the device have low jitter and fast edge rates to optimize the dac noise performance. direct clocking when a high quality, sample rate clock is connected to the ad9148, it provides the lowest noise spectral density at the dac outputs. to select the differential clk inputs as the source for the dac sampling clock, set the pll enable bit to 0 (register 0x0a, bit 7). setting this bit to 0 powers down the internal pll clock multiplier and selects the input from the clk_x pins as the source for the internal dacclk. the device also has duty-cycle correction circuitry and differential input level correction circuitry. enabling these circuits may provide improved performance in some cases. the control bits for these functions can be found in register 0x08. 200 ? 200 ? 100? 5k? 5k? 1000pf 1000pf 1.25v clk_n/ refclk_n clk_p/ refclk_p lvpecl driver dac dac 100? 5k? 5k? 1000pf 1000pf 1.25v clk_n/ refclk_n clk_p/ refclk_p lvds driver 08910-071 figure 72. clock receiver circuitry and recommended drive circuitry using lvpecl (left) and lvds (right)
ad9148 rev. 0 | page 57 of 76 clk_p/clk_n (pin b6 and pin a6) adc vco loop filter refclk_p/refclk_n (pin b9 and pin a9) 0x0e[3:0] pll control voltage 0x0d[1:0] n1 0x0d[3:2] n0 0x0d[7:6] n2 n1 n0 0x06[7:6] pll lock pll lock lost phase detection 0x0a[7] pll enable dacclk pc_clk n2 08910-072 figure 73. pll clock multiplication circuit table 25. pll settings address pll spi control register bit optimal setting pll loop bandwidth 0x0c [7:5] 110 pll control 1 register 0x0c [4:0] 01001 pll cross control enable 0x0d [4] 1 clock multiplication the on-chip pll clock multiplier circuit can be used to generate the dac sample rate clock from a lower frequency reference clock. when the pll clock multiplier is enabled (register 0x0a[7] = 1), the clock multiplication circuit generates the dac sample clock from the lower rate refclk input. the functional diagram of the clock multiplier is shown in figure 73 . the clock multiplication circuit operates such that the vco outputs a frequency, f vco , equal to the refclk input signal frequency multiplied by n0 n1. f vco = f refclk ( n0 n1 ) the dac sample clock frequency, f dacclk , is equal to f dacclk = f refclk n1 the output frequency of the vco must be chosen to keep f vco in the optimal operating range of 1.0 ghz to 2.1 ghz. the frequency of the reference clock and the values of n1 and n0 must be chosen so that the desired dacclk frequency can be synthesized and the vco output frequency is in the correct range. pll bias settings there are four bias settings for the pll circuitry that should be programmed to their nominal values. the pll values shown in table 25 are the recommended settings for these parameters. configuring the vco tuning band the pll vco has a valid operating range from approximately 1.0 ghz to 2.1 ghz covered in 63 overlapping frequency bands. for any desired vco output frequency, there may be several valid pll band select values. th e frequency bands of a typical device are shown in figure 74 . device-to-device variations and operating temperature affect the actual band frequency range. therefore, it is required that the optimal pll band select value be determined for each individual device. 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 1000 2200 2000 1800 1600 1400 1200 pll band vco frequency (mhz) 08910-073 figure 74. pll lock range overtemperature for a typical device automatic vco band select the device has an automatic vco band select feature on chip; using this feature is a simple and reliable method for configuring the vco frequency band. to use the automatic vco band select feature, enable the pll by writing 0xc0 to register 0x0a and enable the auto band select mode by writing 0x80 to register 0x0a. when this value is written, the device executes an automated routine that determines the optimal vco band setting for the device. the setting selected by the device ensures that the pll remains locked over the full ?40c to +85c operating temperature range of the device without further adjustment. (the pll remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes.)
ad9148 rev. 0 | page 58 of 76 manual vco band select th e device also has a manual band select mode that allows the user to select the vco tuning band. when in manual mode (enabled by setting bit 6, register 0x0a to 1), the vco band is set directly with the value written to the manual vco band bit enabled (bits[5:0], register 0x0a). to properly select the vco band, complete the following sequence: 1. put the device in manual band select mode. 2. sweep the vco band over a range of bands that results in the pll being locked. 3. verify that the pll is locked and read the vco control voltage for each band. 4. select the band that results in the control voltage being closest to the center of the range (that is, 1000). see table 26 for more details. the resulting vco band should be the optimal setting for the device. this band should be written to the manual vco band register value. if desired, an indication of where the vco is within the operating frequency band can be determined by querying the vco control voltage. table 26 shows how to interpret the vco control voltage value. table 26. vco control voltage range indications vco control voltage indication 1111 move to a higher vco band. 1110 1101 vco is operating in the higher end of frequency band. 1100 1011 1010 1001 vco is operating with an optimal region of the frequency band. 1000 0111 0110 0101 vco is operating in the lower end of frequency band. 0100 0011 0010 0001 move to a lower vco band. 0000
ad9148 rev. 0 | page 59 of 76 analog outputs transmit dac operation figure 76 shows a simplified block diagram of one pair of the transmit path dacs. the dac core consists of a current source array, switch core, digital control logic, and full-scale output current control. the dac full-scale output current (i outfs ) is nominally 20 ma. the output currents from the ioutx_p and ioutx_n pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. the dac has a 1.2 v band gap reference with an output impedance of 5 k. the reference output voltage appears on the vref pin. when using the internal reference, the vref pin should be decoupled to avss with a 0.1 f capacitor. the internal reference should only be used for external circuits that draw dc currents of 2 a or less. for dynamic loads or static loads greater than 2 a, the vref pin should be buffered. if desired, an external reference (between 1.10 v to 1.30 v) can be applied to the vref pin. a 10 k external resistor, r set , must be connected from the reset pin to avss. this resistor, along with the reference control amplifier, sets up the correct internal bias currents for the dac. because the full-scale current is inversely proportional to this resistor, the tolerance of r set is reflected in the full-scale output amplitude. the full-scale current can be calculated by ? ? ? ? ? ? ? ? ? ? ? ? += dac gain r i set outfs 16 3 72 v ref where dac gain is set individually for the i and q dacs in register 0x30, register 0x31, register 0x34, and register 0x35, respectively. for nominal values of vref (1.2 v), r set (10 k), and dac gain (512), the full-scale current of the dac is typically 20.16 ma. the dac full-scale current can be adjusted from 8.66 ma to 31.66 ma by setting the dac gain parameter setting as shown in figure 75 . 35 0 0 1000 dac gain code i outfs (ma) 30 25 20 15 10 5 200 400 600 800 08910-074 figure 75. dac full-scale cu rrent vs. dac gain code transmit dac transfer function the output currents from the ioutx_p and ioutx_n pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. ioutx_p provides the maximum output current when all bits are high. the output currents vs. daccode for the dac outputs are expressed as outfs n pout i daccode i ? ? ? ? ? ? = 2 _ (1) i out_n = i outfs C i out_p (2) where daccode = 0 to 2 n ? 1. i dac iout1_p/iout3_p iout1_n/iout3_n q dac iout2_n/iout4_n iout2_p/iout4_p current scaling i dac gain q dac gain 0.1 f 10k? i120 vref rset 5k ? 1.2v 08910-075 figure 76. simplified block diagram of the dac core
ad9148 rev. 0 | page 60 of 76 transmit dac output configurations the optimum noise and distortion performance of the ad9148 is realized when it is configured for differential operation. the common-mode error sources of the dac outputs are reduced significantly by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. this is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. iout1_p/iout3_p iout1_n/iout3_n iout2_n/iout4_n iout2_p/iout4_p r o r o v ip + v in ? v outi r o r o v qp + v qn ? v outq 0 8910-076 figure 77. basic transmit dac output circuit figure 77 shows the most basic dac output circuitry. a pair of resistors, r o , are used to convert each of the complementary output currents to a differential voltage output, v out . because the current outputs of the dac are high impedance, the differential driving point impedance of the dac outputs, r out , is equal to 2 r o . figure 78 illustrates the output voltage waveforms. v peak v p time v n v om v p 08910-077 figure 78. voltage output waveforms the common-mode signal voltage, v cm , is calculated by o fs cm r i v = 2 the peak output voltage, v peak , is calculated by v peak = i fs r o with this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. transmit dac linear output signal swing the dac outputs have a linear output compliance voltage range of 1 v that must be adhered to achieve optimum performance. the linear output signal swing is dependent on the full-scale output current, i outfs , and the common-mode level of the output. auxiliary dac operation the ad9148 has four 10-bit auxiliary dacs (aux1, aux2, aux3, and aux4). the full-scale output current on these dacs is derived from the 1.2 v band gap reference and external resistor. the gain scale from the reference amplifier current, i ref , to the auxiliary dac reference current is 16.67 with the auxiliary dac gain set to full-scale. this gives a full-scale current of approximately 2 ma for each auxiliary dac. the magnitude of the aux1 dac current is controlled via bits[1:0], register 0x33 (msbs) and bits[7:0], register 0x32 (lsbs) when dac spi select = 0 (bit 4, register 0x00). the magnitude of the aux2 dac current is controlled via bits[1:0], register 0x37 (msbs) and bits[7:0], register 0x36 (lsbs) when dac spi select = 0 (bit 4, register 0x00). likewise, the magnitudes of aux3 dac current and aux4 dac current are controlled via register 0x33 to register 0x32 and register 0x37 to register 0x36, respectively when dac spi select = 1 (register 0x00, bit[4]). the auxiliary dac structure is shown in figure 79 . there are two output signals on each auxiliary dac. one signal is p, and the other is n. the auxiliary dac outputs are not differential. only one side of the auxiliary dac (p or n) is active at one time. the inactive side goes into a high impedance state (100 k). control of the p side and n side for the auxiliary dacs is via bit 7, register 0x33 and bit 7, register 0x37 (dac spi select is 0 to control aux1 and aux2, and dac spi select is 1 to control aux3 and aux4). aux_p aux_n v b auxdac direction (source/sink) auxdac[9:0] 0ma to 2ma (source) 0ma to 2ma (sink) auxdac sign (p/n) 08910-078 figure 79. auxiliary dac structure
ad9148 rev. 0 | page 61 of 76 baseband filter implementation in addition, the p or n output can act as a current source or a current sink. when sourcing current, the output compliance voltage is 0 v to 1.6 v. when sinking current, the output compliance voltage is 0.8 v to 1.6 v. the auxiliary dac current direction is programmable via bit 6, register 0x33 and bit 6, register 0x37 (dac spi select is 0 to control aux1 and aux2, and dac spi select is 1 to control aux3 and aux4). the choice of sinking or sourcing should be made at circuit design time. there is no advantage to switching between sourcing and sinking current after the circuit is in place. most applications require a baseband anti-imaging filter between the dac and modulator to filter out nyquist images and broadband dac noise. the filter can be inserted between the i-to-v resistors at the dac output and the signal level setting resistor across the modulator input. doing this establishes the input and output impedances for the filter. figure 82 shows a fifth-order low-pass filter. a common-mode choke is used between the i-to-v resistors and the remainder of the filter. this removes the common-mode signal produced by the dac and prevents the common-mode signal from being converted to a differential signal, which would appear as unwanted spurious signals in the output spectrum. the common-mode choke or balun may not be needed if the layout between the dac and iq modulator is optimized and balanced. splitting the second filter capacitor into two and grounding the center point creates a common-mode low-pass filter, providing additional common-mode rejection of high frequency signals. a purely differential filter passes common-mode signals. these auxiliary dacs can be used for local oscillator (lo) cancellation when the dac output is followed by a quadrature modulator. more information and example application circuits are given in the interfacing to modulators section. interfacing to modulators the ad9148 interfaces to the adl537x family with a minimal number of components. an example of the recommended interface circuitry is shown in figure 80 . rbip 50? rbin 50? ibbn ibbp ad9148 adl537x rbqn 50? rbqp 50? rli 100 ? rlq 100 ? iout1_n iout1_p iout2_p iout2_n qbbp qbbn 08910-079 driving the adl5375-15 with the ad9148 the adl5375-15 requires a 1500 mv dc bias and therefore requires a slightly more complex interface than most other analog devices, inc., modulators. it is necessary to level shift the dac output from a 500 mv dc bias to the 1500 mv dc bias that the adl5375-15 requires. level shifting can be achieved with a purely passive network, as shown in figure 81 . in this network, the dc bias of the dac remains at 500 mv, while the input to the adl5375-15 is 1500 mv. note that this passive level shifting network introduces approximately 2 db of loss in the ac signal. figure 80. typical interface circui try between the ad9148 and adl537x family of modulators ibbn ibbp ad9148 adl5375-15 rbip 45.3 ? rbin 45.3 ? rbqn 45.3 ? rbqp 45.3 ? rlip 3480 ? rlin 3480 ? rlqn 3480 ? rlqp 3480 ? iout1_n iout1_p iout2_p iout2_n qbbp qbbn rsin 1k? rsip 1k? rsqn 1k? rsqp 1k? 5v 5v 08910-081 the baseband inputs of the adl537x family require a dc bias of 500 mv. the nominal midscale output current on each output of the dac is 10 ma (1/2 the full-scale current). therefore, a single 50 resistor to ground from each of the dac outputs results in the desired 500 mv dc common-mode bias for the inputs to the adl537x. the signal level can be reduced by the addition of the load resistor in parallel with the modulator inputs (rli, rlq). the peak-to-peak voltage swing of the transmitted signal is [ ] [] + = 2 2 figure 81. passive level shifting network for biasing the adl5375-15 from the ad9148 idac or qdac 50? 50 ? mabact0043 (optional) 33nh 33nh 2pf 56nh 56nh 100 ? 6pf 3pf 3pf 22pf 22pf adl537x 08910-080 figure 82. dac modulator interface with fifth-order, low pass filter
ad9148 rev. 0 | page 62 of 76 reducing lo leakage and unwanted sidebands analog devices modulators can introduce unwanted signals at the lo frequency due to dc offset voltages in the i and q baseband inputs as well as feedthrough paths from the lo input to the output. the lo feedthrough can be nulled by applying the correct dc offset voltages at the dac output. this can be done either by using the auxiliary dacs (register 0x32, register 0x33, register 0x36, and register 0x37) or by using the digital dc offset adjustments (register 0x2c to register 0x2f). using the auxiliary dacs has the advantage that none of the main dac dynamic range is used for performing the dc offset adjustment. the disadvantage is that the common-mode level of the output signal changes as a function of the auxiliary dac current. the opposite is true when the digital offset adjustment is used. good sideband suppression requires both gain and phase matching of the i and q signals. the phase adjust (register 0x28 to register 0x2b) and gain control (register 0x50 and register 0x51) registers can be used to calibrate i and q transmit paths to optimize the sideband suppression. as an alternative to the digital gain scaling, the dac full-scale output current (register 0x30, register 0x31, register 0x34, and register 0x35) can also be adjusted to calibrate the i and q transmit paths; however, changing the dac full-scale output current affects the common-mode voltage level. for more information on correcting imperfections in iq modulators to improve rf signal fidelity, refer to the an-1039 application note .
ad9148 rev. 0 | page 63 of 76 device power dissipation the ad9148 has four supply rails: avdd33, iovdd, dvdd18, and cvdd18. the avdd33 supply powers the dac core circuitry. the power dissipation of the avdd33 supply rail is independent of the digital operating mode and sample rate. the current drawn from the avdd33 supply rail is typically 98 ma (320 mw) when the full-scale current of the four main dacs (dac 1, dac 2, dac 3, and dac 4) is set to the nominal value of 20 ma. changing the full-scale current directly impacts the supply current drawn from the avdd33 rail. for example, if the full-scale current of the four main dacs is changed to 10 ma, the avdd33 supply current drops by 40 ma to 58 ma. the iovdd voltage supplies the serial port i/o pins (sclk, sdio, sdo, csb, tck, tdi, tdo, tms), the reset pin, and the irq pin. the voltage applied to the iovdd pin can range from 1.8 v to 3.3 v. the current drawn by the iovdd supply pin is typically 1 ma. the dvdd18 supply powers all of the digital signal processing blocks of the device. the power consumption from this supply is a function of which digital blocks are enabled and the frequency at which the device is operating. the cvdd18 supply powers the clock receiver and clock distribution circuitry. the power consumption from this supply varies directly with the operating frequency of the device. cvdd18 also powers the pll. the power dissipation of the pll is typically 80 mw. figure 83 to figure 88 detail the power dissipation of the ad9148 under a variety of operating conditions. all of the graphs are taken with data being supplied to all four dacs. the power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or analog output frequency. graphs of the total power dissipation are shown along with the power dissipation of the dvdd18 and cvdd18 supplies. 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 f data (msps) power dissip a tion (w) 1 2 4 8 0 8910-082 figure 83. total power dissipation vs. f data with coarse modulation, pll, and inverse sinc filter disabled 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 f data (msps) power dissip a tion (w) 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 0 8910-083 1 2 4 8 figure 84. total power dissipation vs. f data with fine modulation, pll, and inverse sinc filter disabled 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 f data (msps) power dissip a tion (w) 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 8910-084 1 2 4 8 figure 85. dvdd18 power dissipation vs. f data with coarse modulation, pll, and inverse sinc filter disabled 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 f data (msps) power dissip a tion (w) 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0 8910-085 1 2 4 8 figure 86. dvdd18 power dissipation vs. f data with fine modulation, pll, and inverse sinc filter disabled
ad9148 rev. 0 | page 64 of 76 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0 100 200 300 400 500 600 700 800 900 1000 f dac (msps) power (w) 08910-086 figure 87. cvdd18 power dissipation vs. f dac , pll disabled 0 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 power (w) 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 f data (msps) 08910-087 figure 88. dvdd18 power dissipation vs. f data due to inverse sinc filter
ad9148 rev. 0 | page 65 of 76 temperature sensor the ad9148 has a diode-based temperature sensor for measuring the temperature of the die. the temperature reading is accessed by register 0x5e and register 0x5f. the temperature of the die can be calculated as 130 )700,13]0:15[( ? = dietemp t die where t die is the die temperature in degrees celsius. the temperature accuracy is 5c typical over the +85c to ?35c range. a typical plot of the ad9148 die temperature vs. die temperature code readback is shown in figure 89 . 7,500 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 10,000 12,500 15,000 17,500 20,000 22,500 25,000 27,500 temperature (c) die code readback measured die temperature calculated die temperature +5c ?5c 08910-189 figure 89. die temperature vs. die temperature code readback estimates of the ambient temperature can be made if the power dissipation of the device is known. for example, if the device power dissipation is 800 mw and the measured die temperature is 50c, then the ambient temperature can be calculated as t a = t die C p d t ja = 50 C 0.8 18 = 35.6c where: t a is the ambient temperature in degrees celsius. t ja is the thermal resistance from junction to ambient of the ad9148 as shown in table 7 . to use the temperature sensor, it must be enabled by setting bit 0, register 0x5c to 0. before the temperature sensor data can be read back, it must be latched by toggling bit 1, register 0x5c from 0 to 1. in addition, to get accurate readings, the die temperature control register (register 0x5d) should be set to 0x02.
ad9148 rev. 0 | page 66 of 76 interrupt request operation the ad9148 provides an interrupt request output signal (pin h4, irq ) that can be used to notify an external host processor of significant device events. upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. the irq pin is an open-drain, active low output. pull the irq pin high external to the device. this pin may be tied to the interrupt pins of other devices with open-drain outputs to wired-or these pins together. ten different event flags provide visibility into the device. these 10 flags are located in the two event flag registers (register 0x06 and register 0x07). the behavior of each of the event flags is independently selected in the interrupt enable registers (register 0x04 and register 0x05). when the flag interrupt enable is active, the event flag latches and triggers an external interrupt. when the flag interrupt is disabled, the event flag simply monitors the source signal, and the external irq remains inactive. figure 90 shows the irq -related circuitry. shows how the event flag signals propagate to the figure 90 irq output. the interupt_enable signal represents one bit from the interrupt enable register. the event_flag signal represents one bit from the event flag register. the event_flag_source signal represents one of the device signals that can be monitored such as the pll_locked signal from the pll phase detector or the fifo warning 1 signal from the fifo controller. when an interrupt enable bit is set high, the corresponding event flag bit reflects a positively tripped (that is, latched on the rising edge of the event_flag_source version of the event_flag_source signal. this signal also asserts the external irq . when an interrupt enable bit is set low, the event flag bit reflects the current status of the event_flag_source signal, and the event flag has no effect on the external irq . the latched version of an event flag (the interupt_source signal) can be cleared in two ways. the recommended way is by writing 1 to the corresponding event flag bit. a hardware or software reset also clears the interupt_source. interrupt service routine i nterrupt request management starts by selecting the set of event flags that require host intervention or monitoring. those events that require host action should be enabled so that the host is notified when they occur. for events requiring host intervention, upon irq activation, run the following routine to clear an interrupt request: ? read the status of the event flag bits that are being monitored. ? set the interupt enable bit low so that the unlatched event_flag_source can be monitored directly. ? p erform any actions that may be required to quiet the event_source_flag. in many cases, no specific actions may be required. ? r ead the event flag to verify that the actions taken have quieted the event_flag_source. ? c lear the interrupt by writing 1 to the event flag bit. ? set the interrupt enable bits of the events to be monitored. noted that some of the event_flag_source signals are latched signals. these are cleared by writing to the corresponding event flag bit. details of each of the event flags can be found in table 12 . interrupt_enable event_flag_source device_reset event_flag interrupt source 1 0 other interrupt sources irq w rite_1_to_event_flag 08910-088 figure 90. simplified schematic of irq circuitry
ad9148 rev. 0 | page 67 of 76 interface timing validation the ad9148 provides on-chip sample error detection (sed) circuitry that simplifies verification of the input data interface. the sed compares the input data samples captured at the digital input pins with a set of comparison values. the comparison values are loaded into registers through the spi port. differences between the captured values and the comparison values are detected and stored. options are available for customizing sed test sequencing and error handling. sed operation the sed circuitry operates on two data sets, one for each data port, each made up of four 16-bit input words, denoted as s0, s1, s2, and s3. to properly align the input samples, the first data-word (that is, s0) is indicated by asserting frame for at least one complete input sample. figure 91 shows the input timing of the interface for each port. the frame signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the s0 and s1 data-words. framea/ frameb a[15:0]/ b[15:0] s3 s1 s0 s2 s0 s1 08910-089 figure 91. timing diagram of extend ed frame signal required to align input data for sed the sed has five flag bits (register 0x40, bit 0, bit 1, bit 2, bit 5 and bit 6) that indicate the results of the input sample comparisons. the sample error detected bit (bit 5, register 0x40 for port a and bit 6, register 0x40 for port b) is set when an error is detected and remains set until cleared. the sed also provides registers that indicate which input data bits experienced errors (register 0x41 through register 0x44). these bits are latched and indicate the accumulated errors detected until cleared. the autoclear mode has two effects: it activates the compare fail bits and the compare pass bit (register 0x40, bit 2, bit 1, and bit 0) and changes the behavior of register 0x41 through register 0x44. the compare pass bit sets if the last comparison indicated that the sample was error free. the compare fail bit sets if an error is detected. the compare fail bit is cleared automatically by the reception of eight consecutive error-free comparisons. when autoclear mode is enabled (bit 3, register 0x40), register 0x41 through register 0x44 accumulate errors as previously described but reset to all 0s after eight consecutive error-free sample comparisons are made. the sample error, compare pass, and compare fail flags can be configured to trigger an irq when active, if desired. this is done by enabling the appropriate bits in the event flag register (register 0x07). sed example normal operation th e following example illustrates the sed configuration for continuously monitoring the input data and assertion of an irq when a single error is detected. 1. write to the following registers to enable the sed and load the comparison values: register 0x40 0x80 register 0x00[4] 0 (to configure port a sed) register 0x38 s0[7:0] register 0x39 s0[15:8] register 0x3a s1[7:0] register 0x3b s1[15:8] register 0x3c s2[7:0] register 0x3d s2[15:8] register 0x3e s3[7:0] register 0x3f s3[15:8] register 0x00[4] 1 (to configure port b sed) register 0x38 s0[7:0] register 0x39 s0[15:8] register 0x3a s1[7:0] register 0x3b s1[15:8] register 0x3c s2[7:0] register 0x3d s2[15:8] register 0x3e s3[7:0] register 0x3f s3[15:8] comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test. 2. enable the sed error detect flag to assert the irq pin. r egister 0x05 0x04 3. begin transmitting the input data pattern. if irq is asserted, read register 0x40 and register 0x41 through register 0x44 with bit 4, register 0x00 = 0 for port a and with bit 4, register 0x00 = 1 for port b, to verify that a sed error was detected, and determine which input bits were in error. the bits in register 0x41 through register 0x44 are latched; therefore, the bits indicate any errors that occurred on those bits throughout the test and not just the errors that caused the error detected flag to be set. note that the frame signal is not required during normal operation when the device is configured for dual-port mode. to enable the alignment of the s0 sample as previously described requires the use of both the framea and frameb signals. the timing diagrams for single-port and byte modes are the same as during normal operation and are shown in figure 47 and figure 48 , respectively. for single-port and byte mode, only framea and the irqs for port a should be used. the framea rising edge should always be aligned with the first sample of the data trans- mission. there should not be another rising edge until four complete words of data are received. this means four data samples for dual- port mode and eight data samples for single-port and byte modes.
ad9148 rev. 0 | page 68 of 76 test access port t he ad9148 incorporates a test access port (tap) and boundary scan architecture. the tap has four pins that provide access into the device for performing the boundary scan testing. ? tms, test mode select input ? tck, test clock input ? tdi, test data input ? tdo, test data output the instruction register holds the current instruction used by the tap controller to decide what to do with the test signals that are received. most commonly, the content of the instruction register defines to which of the data registers signals should be passed. table 27 shows the supported instructions, the instruction code, and the data register selected. all instruction codes that are not listed in table 27 are reserved. table 27. instruction code register definition tap instruction instruction code data register selected extest 00000 boundary scan idcode 00001 idcode sample/preload 00010 boundary scan bypass 11111 bypass the boundary scan register is the main test register. it provides the means for moving data from and to the device pins. the bypass register is a single bit register that passes data from tdi to tdo. the idcode register contains the id code and revision number for the device. this information allows the device to be linked to its boundary scan description language (bsdl) file. the file contains details of the boundary scan configuration for the device. the content of the 32-bit idcode register is 0x227e51cb. the tap controller is reset to an inactive state by the internal power-on-reset. figure 92 shows the basic timing diagram of the controller signals. t tck t dsys t ssys t dtdo t stap t htap t hsys tck tms tdi tdo system inputs system outputs 08910-090 figure 92. basic timing diagram of the tap controller signals table 28. parameter description minimum maximum unit timing characteristics t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 4 ns t hsys system inputs hold after tck high 5 ns t trstw tms pulse width to reset tap controller (measured in tck cycles) 5 tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system output delay after tck low 0 12 ns
ad9148 rev. 0 | page 69 of 76 a total of 79 pins can be accessed through the boundary scan register. they are as follows: ? a [15:0]_p, a[15:0]_n, b[15:0]_p, b[15:0]_n ? d cia_p, dcia_n, dcib_p, dcib_n, ? framea_p, framea_n, frameb_p, frameb_n ? reset ? cs , sclk, sdio, sdo ? irq ? pll_lock figure 93 shows the basic connection between the device pins and the boundary scan chain. the boundary scan allows connectivity checks of the device pins but does not allow for stimulating or querying the device core. wh en loading and unloading the ad9148 scan chain, note that ? when unloading the scan chain, if dcia_x or framea_x are set on the pins, there are two bits set for each (bit 42 and bit 44 for dcia_x and bit 41 and bit 43 for framea_x). if dcib_x or frameb_x is set on the pins, there is one bit set for each (bit 42 for dcib_x and bit 41 for frameb_x). ? if the scan chain is used to load the output pins ( irq , sdo, or pll_lock), two bits are set when each output pin is read back. the two bits include the output pin of interest and the bit that is two locations lower on the scan chain (for example, to read back irq , both bit 4 and bit 2 are set). ? the sdioen signal cannot be read back. also, when readback begins, the values of the reset , cs , sclk, and sdio input pins are resampled. if the inputs have changed value since the sampling with the tap preload command, this affects the readback results. the order of the scan chain readback is: sdoen, sdo, pll_lock, irq , sdi_preload, sdio_current, sclk_current, csb_current, reset _current, portb data, porta data, dcis, and frames. chip core input bsr input pad output pad output bsr serial in (tdi) (scan in) scan out (scan out) serial out (tdo) updt_out 08910-091 figure 93. basic connections between device pins and the boundary scan chain
ad9148 rev. 0 | page 70 of 76 for the order of loading and unloading the scan chain, refer to table 29 . table 29. tap load and read sequence tap load sequence tap unload sequence 0 sdioen sdoen 1 sdoen sdo 2 sdo pll_lock 3 pll_lock irq 4 irq sdio, preload 5 sdio sdio, current 6 sclk sclk, current 7 csb csb, current 8 reset reset , current 9 b15_p b15_p 10 b14_p b14_p 11 b13_p b13_p 12 b12_p b12_p 13 b11_p b11_p 14 b10_p b10_p 15 b9_p b9_p 16 b8_p b8_p 17 b7_p b7_p 18 b6_p b6_p 19 b5_p b5_p 20 b4_p b4_p 21 b3_p b3_p 22 b2_p b2_p 23 b1_p b1_p 24 b0_p b0_p 25 a15_p a15_p 26 a14_p a14_p 27 a13_p a13_p 28 a12_p a12_p 29 a11_p a11_p 30 a10_p a10_p 31 a9_p a9_p 32 a8_p a8_p 33 a7_p a7_p 34 a6_p a6_p 35 a5_p a5_p 36 a4_p a4_p 37 a3_p a3_p 38 a2_p a2_p 39 a1_p a1_p 40 a0_p a0_p 41 frameb_p frameb_p 42 dcib_p dcib_p 43 framea_p framea_p 44 dcia_p dcia_p
ad9148 rev. 0 | page 71 of 76 example start-up routine t o ensure reliable start-up of the ad9148, certain sequences should be followed. an example start-up routine using the following device configuration is used for this example. ? f data = 122.88 msps ? interpolation = 4, using hb1 = 00 and hb2 = 000 ? input data = baseband data ? dual port mode with 1 dci ? f out = 140 mhz ? f refclk = 122.88 mhz ? pll = enabled ? fine nco = enabled ? inverse sinc filter = disabled ? synchronization = enabled derived pll settings t he following pll settings can be derived from the device configuration: ? f dacclk = f data interpolation = 491.52 mhz ? f vco = 4 f dacclk = 1966.08 mhz (1 ghz < f vco < 2 ghz) ? n1 = f dacclk /f refclk = 4 ? n0 = f vco /f dacclk = 4 derived nco settings t he following nco settings can be derived from the device configuration: ? f out = 140 mhz ? f dacclk = f data interpolation = 491.52 mhz ? ftw = 140/(491.52) 2 32 = 0x48, eaaaaa start-up sequence t he power clock and register write sequencing for reliable device start-up follows: ? power up the device (no specific power supply sequence is required) ? apply a stable refclk input signal. ? apply a stable dci input signal. ? issue a hardware reset (optional) ? configure device registers with the following write sequence: 0x0c 0xc9 0x0d 0xd9 0x0a 0xc0 0x0a 0x80 0x10 0x48 0x14 0x40 0x17 0x80 0x17 0x00 0x19 0x80 0x19 0x00 0x1c 0x40 0x1d 0x00 0x1e 0x01 0x54 0xaa 0x55 0xaa 0x56 0xea 0x57 0x48 0x5a 0x01 0x5a 0x00 device verification sequence t he following device polling can be conducted to verify that the device is working properly: ? read 0x06, expect bit 7 = 0, bit 6 = 1, bit 5 = 0, bit 4 = 1, bit 2 = 1 ? read 0x12, expect bit 6 = 1 ? read 0x18, expect 0x0f (0x07 is also normal) ? read 0x1a, expect 0x0f (0x07 is also normal)
ad9148 rev. 0 | page 72 of 76 outline dimensions * compliant to jedec standards mo-205-ae with exception to package height. 06-15-2010-a 0.80 bsc 0.80 ref a b c d e f g 9 10 8 11 121314 7 5 642 31 bottom view 10.40 bsc sq h j k l m n p detail a top view detail a coplanarity 0.12 0.50 0.45 0.40 * 1.30 max ball diameter seating plane 12.10 12.00 sq 11.90 a1 ball corner a1 ball corner 0.96 0.70 0.35 nom 0.30 min figure 94. 196-ball chip scale package, ball grid array [csp_bga] bc-196-7 dimensions shown in millimeters
ad9148 rev. 0 | page 73 of 76 compliant to jedec standards mo-192. 03-02-2010-a 0.80 bsc 0.80 ref 0.24 ref 0.75 ref a b c d e f g 9 10 1112 13 14 8 7 5 642 31 bottom view 10.40 bsc sq h j k l m n p detail a top view detail a coplanarity 0.12 0.53 0.48 0.43 ball diameter seating plane 12.10 12.00 sq 11.90 a1 ball pad corner a1 ball pad corner 1.50 1.32 1.17 11.20 ref sq 8.20 sq 1.09 0.99 0.89 0.38 0.33 0.28 figure 95. 196-ball ball grid array, thermally enhanced [bga_ed] bp-196-1 dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9148bbcz ?40c to +85c 196-ball chip scale package ball grid array [csp_bga] bc-196-7 AD9148BBCZRL ?40c to +85c 196-ball chip scale package ball grid array [csp_bga] bc-196-7 ad9148bbpz ?40c to +85c 196-ball ball grid array, thermally enhanced [bga_ed] bp-196-1 ad9148bbpzrl ?40c to +85c 196-ball ball grid ar ray, thermally enhanced [bga_ed] bp-196-1 ad9148-ebz dac only evaluation board [bga_ed] bp-196-1 ad9148-m5372-ebz ad9148 + adl5372 evaluation board [bga_ed] bp-196-1 ad9148-m5375-ebz ad9148 + adl5375-0.5 evaluation board [bga_ed] bp-196-1 1 z = rohs compliant part.
ad9148 rev. 0 | page 74 of 76 notes
ad9148 rev. 0 | page 75 of 76 notes
ad9148 rev. 0 | page 76 of 76 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08910-0-6/10(0)

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